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參數資料
| 型號： | UPD65969 |
| 英文描述： | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| 中文描述： | CMOS門陣列Array.Embedded的包版本2.0 |設計手冊[05/2003] |
| 文件頁數： | 24/64頁 |
| 文件大?。?/td> | 399K |
| 代理商： | UPD65969 |
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24
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
Table 5-3. Standby Mode Setup (HALT #b
3
b
2
b
1
b
0
B) and Release Conditions
Operand Value of
HALT Instruction
Setting Mode
Precondition for Setup
Release Condition
b
3
b
2
b
1
b
0
0
0
0
0
STOP
All K
I/O
pins are high-level output.
High level is input to at least one
of K
I
pins.
0
1
1
STOP
All K
I/O
pins are high-level output.
High level is input to at least one
of K
I
pins.
1
1
0
STOP
Note 1
The K
I/O0
pin is high-level output.
High level is input to at least one
of K
I
pins.
1
Any of the
STOP
[The following condition is added in addition to the above.]
combinations of
—
High level is input to at least one
b
2
b
1
b
0
above
of S
0
, S
1
and S
2
pins
Note 2
.
0/1
1
0
1
HALT
—
When the timer’s down counter is 0
Notes 1.
When setting HALT #
×
110B, configure a key matrix by using the K
I/O0
pin and the K
I
pin so that an
internal reset takes effect at the time of program hang-up.
2.
At least one of the S
0
, S
1
and S
2
pins (the pin used for releasing the standby) must be specified as
follows:
S
0
, S
1
pins : INPUT mode (specified by bits 0 and 2 of the P4 register)
S
2
pin
: Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer
output permit flag are cleared to 0.
3. Write the NOP instruction as the first instruction after STOP mode is released.
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