參數(shù)資料
型號(hào)： UPD65948
英文描述： CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003]
中文描述： CMOS門陣列Array.Embedded的包版本2.0 |設(shè)計(jì)手冊(cè)[05/2003]
文件頁(yè)數(shù)： 39/64頁(yè)
文件大小： 399K
代理商： UPD65948
39
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
9.5 Input/Output Instructions
IN A, P0n
IN A, P1n
<1> Instruction code
<2> Cycle count
<3> Function
:
1 1 1 1 P
4
1 1 P
2
P
1
P
0
: 1
: (A)
←
(Pmn)
CY
←
0
m = 0, 1
n = 0, 1, 3, 4
The port Pmn data is loaded (read) onto the accumulator.
OUT P0n, A
OUT P1n, A
<1> Instruction code
<2> Cycle count
<3> Function
The accumulator contents are transferred to port Pmn to be latched.
:
0 0 1 0 P
4
1 1 P
2
P
1
P
0
: 1
: (Pmn)
←
(A)
m = 0, 1
n = 0, 1, 3, 4
ANL A, P0n
ANL A, P1n
<1> Instruction code
<2> Cycle count
<3> Function
:
1 1 0 1 P
4
1 1 P
2
P
1
P
0
: 1
: (A)
←
(A)
CY
←
A
3
Pmn
∨
(Pmn)
m = 0, 1
n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are ANDed and the results are entered in the
accumulator.
ORL A, P0n
ORL A, P1n
<1> Instruction code
<2> Cycle count
<3> Function
:
1 1 1 0 P
4
1 1 P
2
P
1
P
0
: 1
: (A)
←
(A)
∨
(Pmn)
CY
←
0
m = 0, 1
n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are ORed and the results are entered in the
accumulator.
XRL A, P0n
XRL A, P1n
<1> Instruction code
<2> Cycle count
<3> Function
:
1 0 1 0 P
4
1 1 P
2
P
1
P
0
: 1
: (A)
←
(A)
∨
(Pmn)
CY
←
A
3
Pmn
m = 0, 1
n = 0, 1, 3, 4
The accumulator contents and the port Pmn contents are exclusive-ORed and the results are entered
in the accumulator.
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