參數(shù)資料
型號(hào)： UPD65658-QFP120P1.2SQ
英文描述： ASIC
中文描述： 專用集成電路
文件頁(yè)數(shù)： 24/64頁(yè)
文件大?。?/td> 399K
代理商： UPD65658-QFP120P1.2SQ
24
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
Table 5-3. Standby Mode Setup (HALT #b
3
b
2
b
1
b
0
B) and Release Conditions
Operand Value of
HALT Instruction
Setting Mode
Precondition for Setup
Release Condition
b
3
b
2
b
1
b
0
0
0
0
0
STOP
All K
I/O
pins are high-level output.
High level is input to at least one
of K
I
pins.
0
1
1
STOP
All K
I/O
pins are high-level output.
High level is input to at least one
of K
I
pins.
1
1
0
STOP
Note 1
The K
I/O0
pin is high-level output.
High level is input to at least one
of K
I
pins.
1
Any of the
STOP
[The following condition is added in addition to the above.]
combinations of
—
High level is input to at least one
b
2
b
1
b
0
above
of S
0
, S
1
and S
2
pins
Note 2
.
0/1
1
0
1
HALT
—
When the timer’s down counter is 0
Notes 1.
When setting HALT #
×
110B, configure a key matrix by using the K
I/O0
pin and the K
I
pin so that an
internal reset takes effect at the time of program hang-up.
2.
At least one of the S
0
, S
1
and S
2
pins (the pin used for releasing the standby) must be specified as
follows:
S
0
, S
1
pins : INPUT mode (specified by bits 0 and 2 of the P4 register)
S
2
pin
: Use of STOP mode release enabled (specified by bit 3 of the P4 register)
Cautions 1. The internal reset takes effect when the HALT instruction is executed with an operand value
other than that above or when the precondition has not been satisfied when executing the
HALT instruction.
2. If STOP mode is set when the timer’s down counter is not 0 (timer operating), the system
is placed in STOP mode only after all the 10 bits of the timer’s down counter and the timer
output permit flag are cleared to 0.
3. Write the NOP instruction as the first instruction after STOP mode is released.
相關(guān)PDF資料
PDF描述
UPD65658-QFP160P1.2SQ ASIC
UPD65664-QFP120P1.2SQ ASIC
UPD65664-QFP160P1.2SQ ASIC
UPD65672-QFP120P1.2SQ ASIC
UPD65672-QFP160P1.2SQ ASIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UPD65658-QFP160P1.2SQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
UPD65664 制造商:NEC 制造商全稱:NEC 功能描述:CMOS-6/6A/6V/6X 1.0-MICRON CMOS GATE ARRAYS
UPD65664GN-107-LGT 制造商:Renesas Electronics Corporation 功能描述:
UPD65664-QFP120P1.2SQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
UPD65664-QFP160P1.2SQ 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*