參數(shù)資料
型號(hào)： UPD65567
英文描述： CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003]
中文描述： CMOS門陣列Array.Embedded的包版本2.0 |設(shè)計(jì)手冊(cè)[05/2003]
文件頁(yè)數(shù)： 36/64頁(yè)
文件大?。?/td> 399K
代理商： UPD65567
36
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
9.4 Accumulator Operation Instructions
ANL A, R0n
ANL A, R1n
<1> Instruction code
<2> Cycle count
<3> Function
:
1 1 0 1 R
4
0 R
3
R
2
R
1
R
0
: 1
: (A)
←
(A)
CY
←
A
3
Rmn
3
∨
(Rmn)
m = 0, 1
n = 0 to F
The accumulator contents and the register Rmn contents are ANDed and the results are entered in the
accumulator.
ANL A, @R0H
ANL A, @R0L
<1> Instruction code
<2> Cycle count
<3> Function
:
1 1 0 1 0/1 1 0 0 0 0
: 1
: (A)
←
(A)
CY
←
A
3
ROM
7
(A)
←
(A)
CY
←
A
3
ROM
3
∨
((P13), (R0))
7-4
(in the case of ANL A, @R0H)
∨
((P13), (R0))
3-0
(in the case of ANL A, @R0L)
The accumulator contents and the program memory contents specified with the control register P13 and
register pair R
10
-R
00
are ANDed and the results are entered in the accumulator.
If H is specified, b
7
, b
6
, b
5
and b
4
take effect. If L is specified, b
3
, b
2
, b
1
and b
0
take effect.
Program memory (ROM) organization
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
H
↓
L
↓
Valid bits at the time of accumulator operation
ANL A, #data4
<1> Instruction code
:
1 1 0 1 1 1 0 0 0 1
0 0 0 0 0 0 d
3
d
2
d
1
d
0
: 1
: (A)
←
(A)
CY
←
A
3
data4
3
<2> Cycle count
<3> Function
∨
data4
The accumulator contents and the immediate data are ANDed and the results are entered in the
accumulator.
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