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參數(shù)資料
| 型號： | UPD65365 |
| 英文描述： | CMOS Gate Array.Embedded Array Ver.2.0 for Package | Design Manual[05/2003] |
| 中文描述： | CMOS門陣列Array.Embedded的包版本2.0 |設(shè)計手冊[05/2003] |
| 文件頁數(shù)： | 26/64頁 |
| 文件大小： | 399K |
| 代理商： | UPD65365 |
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26
μ
PD64A, 65
Data Sheet U14380EJ2V0DS00
6. RESET
The system reset takes effect by means of the causes as follows:
When the POC circuit has detected low-power voltage
When the operand value is illegal or does not satisfy the precondition when the HALT instruction is executed
When the accumulator is 0H when the RLZ instruction is executed
When stack pointer overflows or underflows
Table 6-1. Hardware Statuses after Reset
Hardware
Resetting by Internal POC Circuit in Operation
Resetting by Other Factors
Note 1
Resetting by the Internal POC Circuit during
STANDBY Mode
PC (11 bits)
000H
SP (1 bit)
0B
Data
R0 = DP
000H
memory
R1-RF
Undefined
Previous status retained
Accumulator (A)
Undefined
Status flag (F)
0B
Carry flag (CY)
0B
Timer (10 bits)
000H
Port register
P0
FFH
P1
××××
11
×
1B
Note 2
03H
26H
Control register P3
P4
Notes 1.
The following resets are available.
Reset when executing the HALT instruction (when the operand value is illegal or does not satisfy
the precondition)
Reset when executing the RLZ instruction (when A = 0)
Reset by stack pointer’s overflow or underflow
2.
Refers to the value by the K
I
or S
2
pin status.
In order to prevent malfunction, be sure to input a low level to more than one of pins K
I0
to K
I3
when
POC is released due to supply voltage startup.
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