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參數(shù)資料
| 型號(hào)： | UPD6454GT-101 |
| 英文描述： | On-Screen Display Circuit |
| 中文描述： | 屏幕顯示電路 |
| 文件頁(yè)數(shù)： | 29/68頁(yè) |
| 文件大?。?/td> | 301K |
| 代理商： | UPD6454GT-101 |
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29
μ
PD63, 63A, 64
8. SYSTEM CLOCK OSCILLATION CIRCUIT
The system clock oscillation circuit consists of oscillation circuits for ceramic resonators (f
X
= 2.4 to 8 MHz).
Figure 8-1. System Clock
The system clock oscillation circuit stops its oscillation when reset or in STOP mode.
Caution When using the system clock oscillation circuit, wire area indicated by the dotted-line in the
diagram as follows to reduce the effects of the wiring capacitance, etc.
Make the wiring as short as possible.
Do not allow the wiring to intersect other signal lines. Do not wire close to lines through
which large fluctuating currents flow.
Make sure that the point where the oscillation circuit capacitor is installed is always at the
same electric potential as the ground. Never earth with a ground pattern through which large
currents flow.
Do not extract signals from the oscillation circuit.
PD63, 63A, 64
μ
X
OUT
X
IN
GND
Ceramic resonator
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