參數(shù)資料
型號(hào)： UPD61012
英文描述： Consumer IC
中文描述： 消費(fèi)性IC
文件頁(yè)數(shù)： 13/36頁(yè)
文件大?。?/td> 252K
代理商： UPD61012
μ
PD61P24
13
13. CONTROL REGISTER (P
1
)
The control register contains of 10 bits. The controllable items are shown in Table 13-1.
Table 13-1. Control Register (P
1
)
Bit
D
9
Name
Test mode
–
Be sure to set 0.
0
1
Set
Value
Timer
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
HALT
D.P.
AD
MOD
K
I/O
9
D.P.
AD
8
RL A
A
CC
0
←
STOP
NOP
f /8
OSC
AD =0
9
AD =0
8
IN
RUN
OSC
STOP
f /12
OSC
AD =1
9
AD =1
8
OUT
A
3
S-IN
D
0 ..........................
Specifies data to be input to A
0
when the accumulator is shifted to the left.
0: A
3
, 1:S-IN
D
1 ..........................
Specifies the status of K
I/O
, as follows:
0: input mode, 1: output mode
D
2 ..........................
Specifies the status of the timer, as follows:
0: Count stop, 1: Count execution
D
3 ..........................
Specifies the carrier frequency output from the REM pin.
0: f
OSC
/8, 1: f
OSC
/12
D
4
, D
5 .................
Specify the high-order 2 bits of the ROM data pointer.
D
6 ..........................
Determines what happen to the oscillation circuit when the HALT instruction is executed.
0: Oscillation does not stop
1: Oscillation stops (STOP mode)
D
7 ..........................
Be sure to set this bit to 0.
D
8
, D
9 .................
These bits specify test modes. Be sure to set them to 0.
Remark
D
0
= D
8
= D
9
= 0 on reset, and the other bits are undefined.
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