- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379500 > UPD488448FB-C60-53-DQ1 (NEC Corp.) 128 M-bit Direct Rambus⑩ DRAM PDF資料下載
參數(shù)資料
| 型號： | UPD488448FB-C60-53-DQ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 128 M-bit Direct Rambus⑩ DRAM |
| 中文描述： | 128 M位DRAM的直接Rambus的⑩ |
| 文件頁數(shù)： | 19/80頁 |
| 文件大?。?/td> | 1902K |
| 代理商： | UPD488448FB-C60-53-DQ1 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁當前第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁
Data Sheet M14837EJ3V0DS00
19
μ
PD488448 for Rev. P
7. ROW-to-COL Packet Interaction
Figure 7-1 shows two packets on the ROW and COL pins. They must be separated by an interval t
RCDELAY
which
depends upon the packet contents.
Figure 7-1 ROW-to-COL Packet Interaction- Timing
CTM/CFM
DQA7..0
DQB7..0
COL4
..COL0
ROW2
..ROW0
T
0
T
4
T
8
T
12
T
1
T
5
T
9
T
13
T
2
T
6
T
10
T
14
T
3
T
7
T
11
T
15
T
16
T
T
17
T
18
T
19
Transaction a: ROPa
Transaction b: COPb
a0 = {Da,Ba,Ra}
b1= {Db,Bb,Cb1}
t
RCDELAY
ROPa a0
COPb b1
Table 7-1 summarizes the t
RCDELAY
values for all possible cases. Note that if the COL packet is earlier than the
ROW packet, it is considered a COL-to-ROW packet interaction.
Cases RC1 through RC5 summarize the rules when the ROW packet has an ACT command. Figure 13-1 and
Figure 14-1 show examples of RC5 - an activation followed by a read or write. RC4 is an illegal situation, since a
read or write of a precharged banks is being attempted (remember that for a bank to be activated, adjacent banks
must be precharged). In cases RC1, RC2, and RC3, there is no interaction of the ROW and COL packets.
Cases RC6 through RC8 summarize the rules when the ROW packet has a PRER command. There is either no
interaction (RC6 through RC9) or an illegal situation with a read or write of a precharged bank (RC9).
The COL pins can also schedule a precharge operation with a RDA, WRA, or PREC command in a COLC packet or
a PREX command in a COLX packet. The constraints of these precharge operations may be converted to equivalent
PRER command constraints using the rules summarized in Figure 12-2.
Table 7-1 ROW-to-COL Packet Interaction - Rules
Case # ROPa Da
Ba
Ra
COPb
Db
Bb
Cb1
t
RCDELAY
Example
RC1
RC2
RC3
RC4
RC5
ACT
ACT
ACT
ACT
ACT
Da
Da
Da
Da
Da
Ba
Ba
Ba
Ba
Ba
Ra
Ra
Ra
Ra
Ra
NOCOP, RD, retire
NOCOP
RD, retire
RD, retire
RD, retire
/= Da
== Da
== Da
== Da
== Da
xxxx
xxxx
/= {Ba, Ba+1, Ba-1}
== {Ba+1, Ba-1}
== {Ba}
x..x
x..x
x..x
x..x
x..x
0
0
0
Illegal
t
RCD
Figure 13-1
RC6
RC7
RC8
RC9
PRER Da
PRER Da
PRER Da
PRER Da
Ba
Ba
Ba
Ba
Ra
Ra
Ra
Ra
NOCOP, RD, retire
NOCOP
RD, retire
RD, retire
/= Da
== Da
== Da
== Da
xxxx
xxxx
/= {Ba, Ba+1, Ba-1}
== {Ba+1, Ba-1}
x..x
x..x
x..x
x..x
0
0
0
Illegal
相關PDF資料 |
PDF描述 |
|---|---|
| UPD488448FB-C80-45-DQ1 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C80-45-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C71-45-DQ1 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C71-45-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
| UPD488448FB-C60-53-DQ2 | 128 M-bit Direct Rambus⑩ DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| UPD4990AG-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD4991ACX-A | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD4992CX-A | 制造商:Renesas Electronics 功能描述:Cut Tape |
| UPD50256CP15 | 制造商:HIT 功能描述:50256 HITACHI'86 SMT N9F8A |
| UPD50256CP-15 | 制造商:HIT 功能描述:50256 HITACHI'86 SMT N9F8A |
發(fā)布緊急采購，3分鐘左右您將得到回復。