參數(shù)資料
型號(hào)： UPD488448FB-C60-53-DQ1
廠商： NEC Corp.
英文描述： 128 M-bit Direct Rambus⑩ DRAM
中文描述： 128 M位DRAM的直接Rambus的⑩
文件頁(yè)數(shù)： 64/80頁(yè)
文件大小： 1902K
代理商： UPD488448FB-C60-53-DQ1
Data Sheet M14837EJ3V0DS00
64
μ
PD488448 for Rev. P
The SCK clock is also used for sampling data on RSL input in one situation. Figure23-4 shows the PDN and NAP
exit sequences. If the PSX field of the INIT register is one (Figure 22-1 control registers (1/7) “INIT Register”), then
the PDN and NAP exit sequences are broadcast; i.e. all RDRAMs that are in PDN or NAP will perform the exit
sequence. If the PSX field of the INIT register is zero, then the PDN and NAP exit sequences are directed; i.e. only
one RDRAM that is in PDN or NAP will perform the exit sequence.
The address of that RDRAM is specified on the DQA[5:0] bus in the set hold window t
S3
/t
H3
around the rising edge of
SCK. This is shown Figure 33-2. The SCK timing point is measured at the 50 % level, and the DQA [5:0] bus signals
are measured at the V
REF
level.
Figure 33-2 CMOS Timing - Device Address for NAP or PDN Exit
V
IH,CMOS
80%
50%
20%
V
IL,CMOS
SCK
PDEV
V
DIH
80%
20%
V
DIL
DQA[5:0]
V
t
S3
t
H3
REF
相關(guān)PDF資料
PDF描述
UPD488448FB-C80-45-DQ1 128 M-bit Direct Rambus⑩ DRAM
UPD488448FB-C80-45-DQ2 128 M-bit Direct Rambus⑩ DRAM
UPD488448FB-C71-45-DQ1 128 M-bit Direct Rambus⑩ DRAM
UPD488448FB-C71-45-DQ2 128 M-bit Direct Rambus⑩ DRAM
UPD488448FB-C60-53-DQ2 128 M-bit Direct Rambus⑩ DRAM
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