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參數(shù)資料
| 型號： | UPD4704 |
| 廠商： | NEC Corp. |
| 元件分類： | 通用總線功能 |
| 英文描述： | EXTENSION 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS |
| 中文描述： | 延展8位加/減計數(shù)器CMOS集成電路 |
| 文件頁數(shù)： | 5/16頁 |
| 文件大?。?/td> | 191K |
| 代理商： | UPD4704 |
5
μ
PD4704
UP/DOWN
STB
t
SUDSTB1
t
SUDSTB2
If STB changes from "H" to "L" and a reset is
executed in this period, the latch is also reset.
Post-count value latched
Pre-count value latched
Either pre- or post-count value latched
UP/DOWN
STB
RESET
t
SUDSTB1
t
DUDCD
Fig. 2 Relation Between STB Timing and Counter Value
Fig. 3 STB and RESET Timing
(3)
Carry & borrow outputs
If the counter performs an up-count operation when the count value is 0FF
H
, an active-low pulse is output to the
Carry output (the pulse width is virtually the same as the UP or DOWN pulse L period). Similarly, if the counter
performs a down-count operation when the count value is 00
H
, an active-low pulse is output to the Borrow output.
A Borrow pulse is also output if a down-count operation is performed while RESET is "H" (during a reset), and
therefore, when a
μ
PD4704 is added, a reset must be executed at the same time.
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PDF描述 |
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| UPD4704C | EXTENSION 8-BIT UP/DOWN COUNTER CMOS INTEGRATED CIRCUITS |
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