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參數(shù)資料
| 型號(hào)： | UPD4632312A-X |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-BIT CMOS MOBILE SPECIFIED RAM 2M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 32兆位CMOS移動(dòng)指明內(nèi)存200萬字由16位溫度范圍 |
| 文件頁數(shù)： | 17/36頁 |
| 文件大小： | 320K |
| 代理商： | UPD4632312A-X |
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Preliminary Data Sheet M15874EJ5V0DS
17
μ
PD4632312A-X
Read Cycle
Parameter
Symbol
-B60X
-B65X
-BE75X
-BE85X
Unit
Note
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
MIN.
MAX.
Read cycle time
t
RC
65
65
75
85
ns
1
Address access time
t
AA
60
65
75
85
ns
/CS access time
t
ACS
63
65
75
85
ns
/OE to output valid
t
OE
45
45
50
55
ns
/LB, /UB to output valid
t
BA
63
65
75
85
ns
Output hold from address change
t
OH
5
5
5
5
ns
Page read cycle time
t
PRC
18
18
25
30
ns
Page access time
t
PAA
18
18
25
30
ns
/CS to output in low impedance
t
CLZ
10
10
10
10
ns
2
/OE to output in low impedance
t
OLZ
5
5
5
5
ns
/LB, /UB to output in low impedance
t
BLZ
5
5
5
5
ns
/CS to output in high impedance
t
CHZ
25
25
25
25
ns
/OE to output in high impedance
t
OHZ
25
25
25
25
ns
/LB, /UB to output in high impedance
t
BHZ
25
25
25
25
ns
Address set to /OE low level
t
ASO
0
0
0
0
ns
/OE high level to address hold
t
OHAH
–5
–5
–5
–5
ns
/CS high level to address hold
t
CHAH
0
0
0
0
ns
3
/LB, /UB high level to address hold
t
BHAH
0
0
0
0
ns
3, 4
/CS low level to /OE low level
t
CLOL
0
10,000
0
10,000
0
10,000
0
10,000
ns
5
/OE low level to /CS high level
t
OLCH
45
45
50
55
ns
/CS high level pulse width
t
CP
10
10
10
10
ns
/LB, /UB high level pulse width
t
BP
10
10
10
10
ns
/OE high level pulse width
t
OP
2
10,000
2
10,000
2
10,000
2
10,000
ns
5
Notes 1.
Output load: 30 pF
2.
Output load: 5 pF
3.
When t
ASO
≥
| t
CHAH
|, | t
BHAH
|, t
CHAH
and t
BHAH
(MIN.) are –15 ns.
t
CHAH
, t
BHAH
t
ASO
/LB, /UB, /CS (Input)
Address (Input)
/OE (Input)
4.
t
BHAH
is specified from when both /LB and /UB become high level.
5.
t
CLOL
and t
OP
(MAX.) are applied while /CS is being hold at low level.
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