參數(shù)資料
型號(hào)： UPD4632312A-X
廠商： NEC Corp.
英文描述： 32M-BIT CMOS MOBILE SPECIFIED RAM 2M-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION
中文描述： 32兆位CMOS移動(dòng)指明內(nèi)存200萬(wàn)字由16位溫度范圍
文件頁(yè)數(shù)： 12/36頁(yè)
文件大小： 320K
代理商： UPD4632312A-X
Preliminary Data Sheet M15874EJ5V0DS
12
μ
PD4632312A-X
4. Mode Register Settings
The partial refresh density can be set using the mode register. Since the initial value of the mode register at power
application is undefined, be sure to set the mode register after initialization at power application. When setting the
density of partial refresh, data before entering the partial refresh mode is not guaranteed. (This is the same for re-
setup.) However, since partial refresh mode is not entered unless MODE = L when partial refresh is not used, it is not
necessary to set the mode register. Moreover, when using page read without using partial refresh, it is not necessary to
set the mode register.
4.1 Mode Register Setting Method
The mode register setting mode can be entered by successively writing two specific data after two continuous reads of
the highest address (1FFFFFH). The mode register setting is a continuous four-cycle operation (two read cycles and two
write cycles).
Commands are written to the command register. The command register is used to latch the addresses and data
required for executing commands, and it does not have an exclusive memory area.
For the timing chart and flow chart, refer to
Figure 6-12. Mode Register Setting Timing Chart
,
Figure 6-13. Mode
Register Setting Flow Chart
.
Table 4-1. shows the commands and command sequences.
Table 4-1. Command sequence
Command sequence
1st bus cycle
2nd bus cycle
3rd bus cycle
4th bus cycle
(Read cycle)
(Read cycle)
(Write cycle)
(Write cycle)
Partial refresh density
Address
Data
Address
Data
Address
Data
Address
Data
16M bits
1FFFFFH
–
1FFFFFH
–
1FFFFFH
00H
1FFFFFH
04H
8M bits
1FFFFFH
–
1FFFFFH
–
1FFFFFH
00H
1FFFFFH
05H
4M bits
1FFFFFH
–
1FFFFFH
–
1FFFFFH
00H
1FFFFFH
06H
0M bit
1FFFFFH
–
1FFFFFH
–
1FFFFFH
00H
1FFFFFH
07H
4th bus cycle (Write cycle)
I/O
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Mode Register setting
0
0
0
0
0
0
0
0
0
0
0
0
0
PL
PD
Page length
1
8 words
I/O1
I/O0
Density
Partial refresh
0
0
16M bits
density
0
1
8M bits
1
0
4M bits
1
1
0M bit
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