
Preliminary Data Sheet M17507EJ2V0DS
42
μ
PD46128512-X
Figure 7-9. Asynchronous Read Cycle Timing Chart 7 (/LB, /UB Controlled)
/CE1 (Input)
Address (Input)
DQ (Output)
High-Z
High-Z
High-Z
t
RC
/OE (Input)
t
RC
A1
A2
A3
/LB, /UB (Input)
t
BA
t
BHZ
t
BLZ
t
BA
t
BHZ
t
BLZ
t
BP
t
BP
L
L
t
AA
t
AA
t
AX
t
AX
Data Out Q2
Data Out Q1
Cautions 1. In read cycle, CE2 and /WE should be fixed HIGH.
2. /ADV should be fixed LOW or toggled HIGH
→
LOW
→
HIGH. CLK should be fixed HIGH or LOW.
Figure 7-10. Asynchronous Page Read Cycle Timing Chart
DQ (Output)
Address
(A4-A22) (Input)
Page Address
(A0-A3) (Input)
/CE1 (Input)
/OE (Input)
t
PRC
t
PRC
t
PRC
t
RC
t
PAA
t
OH
t
PAA
t
OH
t
PAA
t
OH
t
AA
t
OE
t
OH
A
N+1
A
N+2
A
N+3
A
N+7
Q
N
Q
N+1
Q
N+2
Q
N+3
Q
N+7
t
CHZ
t
OHZ
A
N
t
PAA
t
OH
t
PRC
t
PAA
t
OH
t
PRC
t
PAA
t
OH
t
PRC
t
PAA
t
OH
Q
N+4
Q
N+5
Q
N+6
A
N+4
A
N+5
A
N+6
t
PRC
High-Z
t
ASO
Cautions 1. In read cycle, CE2 and /WE should be fixed HIGH.
2. /LB and /UB should be fixed LOW.
3. /ADV should be fixed LOW. CLK should be fixed HIGH or LOW.
4. Fix /CE1 and /OE to LOW throughout a page operation.
5. Arbitrary order and combination of A0-A3 is possible in the page operation.