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參數(shù)資料
| 型號： | UPD4482321GF-A65-A |
| 元件分類： | SRAM |
| 英文描述： | 256K X 32 CACHE SRAM, 6.5 ns, PQFP100 |
| 封裝： | 14 X 20 MM, PLASTIC, LQFP-100 |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 370K |
| 代理商： | UPD4482321GF-A65-A |
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8
PD4482161, 4482181, 4482321, 4482361
Data Sheet M14521EJ3V0DS
Block Diagrams
[
PD4482161, PD4482181]
Address
register
Binary
counter
and logic
CLR
Q0
Q1
Byte 1
Write register
Byte 1
Write driver
8/9
Byte 2
Write register
Byte 2
Write driver
8/9
Enable
register
Row and column
Input
register
Output
buffer
19
17
19
A0, A1
A1’
A0’
2
16/18
A0 to A18
MODE
/ADV
CLK
/AC
/AP
/BW1
/BW2
/BWE
/GW
/CE
CE2
/CE2
/G
I/O1 to I/O16
I/OP1 to I/OP2
ZZ
Power down control
16/18
Memory cell array
1,024 rows
512
× 16 columns
(8,388,608 bits)
512
× 18 columns
(9,437,184 bits)
decoders
Burst Sequence
[
PD4482161, PD4482181]
Interleaved Burst Sequence Table (MODE = VDD)
External Address
A18 to A2, A1, A0
1st Burst Address
A18 to A2, A1, /A0
2nd Burst Address
A18 to A2, /A1, A0
3rd Burst Address
A18 to A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
1st Burst Address
A18 to A2, 0, 1
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
2nd Burst Address
A18 to A2, 1, 0
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
3rd Burst Address
A18 to A2, 1, 1
A18 to A2, 0, 0
A18 to A2, 0, 1
A18 to A2, 1, 0
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| UPD45128163G5 | 制造商:Renesas Electronics Corporation 功能描述:128 MBIT SDRAM |
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| UPD45128841G5-A75-9JF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 16M x 8, 54 Pin, Plastic, TSOP |
| UPD4516161AG5A109NF | 制造商:NEC Electronics Corporation 功能描述: |
| UPD4516161AG5-A10-9NF | 制造商:NEC Electronics Corporation 功能描述:SDRAM, 1M x 16, 50 Pin, Plastic, TSOP |
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