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參數(shù)資料
| 型號(hào)： | UPD444012AGY-C85X-MJH |
| 廠商： | NEC Corp. |
| 英文描述： | 4M-BIT CMOS STATIC RAM 256K-WORD BY 16-BIT EXTENDED TEMPERATURE OPERATION |
| 中文描述： | 4分位CMOS靜態(tài)RAM 256K字由16位溫度范圍 |
| 文件頁數(shù)： | 12/24頁 |
| 文件大?。?/td> | 143K |
| 代理商： | UPD444012AGY-C85X-MJH |
Data Sheet M14464EJ5V0DS
12
μ
PD444012A-X
Write Cycle Timing Chart 1 (/WE Controlled)
t
WC
t
CW1
t
BW
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High
impe-
dance
High
impe-
dance
Data in
Indefinite data out
Address (Input)
/CE1 (Input)
/LB, /UB (Input)
I/O (Input / Output)
CE2 (Input)
t
CW2
t
AW
t
WP
t
AS
t
WR
/WE (Input)
Cautions 1. During address transition, at least one of pins /CE1, CE2, /WE should be inactivated.
2. Do not input data to the I/O pins while they are in the output state.
Remarks 1.
Write operation is done during the overlap time of a low level /CE1, /WE, /LB and/or /UB, and a
high level CE2.
2.
If /CE1 changes to low level at the same time or after the change of /WE to low level, or if CE2
changes to high level at the same time or after the change of /WE to low level, the I/O pins will
remain high impedance state.
3.
When /WE is at low level, the I/O pins are always high impedance. When /WE is at high level,
read operation is executed. Therefore /OE should be at high level to make the I/O pins high
impedance.
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