參數(shù)資料
型號(hào)： UPD44325082F5-E40-EQ2
廠商： NEC Corp.
英文描述： 36M-BIT QDRII SRAM 2-WORD BURST OPERATION
中文描述： 36M條位推出QDRII SRAM的2字爆發(fā)運(yùn)作
文件頁(yè)數(shù)： 12/32頁(yè)
文件大小： 357K
代理商： UPD44325082F5-E40-EQ2
12
Preliminary Data Sheet
M16783EJ1V0DS
μ
PD44325082, 44325092, 44325182, 44325362
[
μ
PD44325362]
Operation
K
/K
/BW0
/BW1
/BW2
/BW3
Write D0 to D35
L
→
H
–
–
0
0
0
0
L
→
H
–
0
0
0
0
Write D0 to D8
L
→
H
–
0
1
1
1
L
→
H
–
0
1
1
1
Write D9 to D17
L
→
H
–
1
0
1
1
L
→
H
–
1
0
1
1
Write D18 to D26
L
→
H
–
1
1
0
1
L
→
H
–
1
1
0
1
Write D27 to D35
L
→
H
–
1
1
1
0
L
→
H
–
1
1
1
0
Write nothing
L
→
H
–
1
1
1
1
L
→
H
1
1
1
1
Remarks 1.
H : High level, L : Low level,
→
: rising edge.
2.
Assumes a WRITE cycle was initiated. /BW0 to /BW3 can be altered for any portion of the BURST
WRITE operation provided that the setup and hold requirements are satisfied.
Bus Cycle State Diagram
READ DOUBLE
WRITE DOUBLE
AT /K
Power UP
Always
Supply voltage
provided
LOAD NEW
READ ADDRESS
READ PORT NOP
R_Init = 0
WRITE PORT NOP
LOAD NEW
WRITE ADDRESS
AT /K
Always
/W = L
Supply voltage
provided
/W = L
/W = H
/W = H
/R = L
/R = L
/R = H
/R = H
Remarks 1.
The address is concatenated with 1 additional internal LSB to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2.
Read and write state machines can be active simultaneously.
3.
State machine control timing sequence is controlled by K.
相關(guān)PDF資料
PDF描述
UPD44325182F5-E40-EQ2 36M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44325362F5-E40-EQ2 36M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44325082 36M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44325092F5-E50-EQ2 36M-BIT QDRII SRAM 2-WORD BURST OPERATION
UPD44325182F5-E50-EQ2 36M-BIT QDRII SRAM 2-WORD BURST OPERATION
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