- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379497 > UPD44325082 (NEC Corp.) 36M-BIT QDRII SRAM 2-WORD BURST OPERATION PDF資料下載
參數(shù)資料
| 型號(hào)： | UPD44325082 |
| 廠商： | NEC Corp. |
| 英文描述： | 36M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| 中文描述： | 36M條位推出QDRII SRAM的2字爆發(fā)運(yùn)作 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 357K |
| 代理商： | UPD44325082 |
當(dāng)前第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
The mark shows major revised points.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
MOS INTEGRATED CIRCUIT
μ
PD
44325082, 44325092, 44325182, 44325362
36M-BIT QDR
TM
II SRAM
2-WORD BURST OPERATION
Document No. M16783EJ1V0DS00 (1st edition)
Date Published October 2004 NS CP(K)
Printed in Japan
PRELIMINARY DATA SHEET
2003
Description
The
μ
PD44325082 is a 4,194,304-word by 8-bit, the
μ
PD44325092 is a 4,194,304-word by 9-bit, the
μ
PD44325182 is a
2,097,152-word by 18-bit and the
μ
PD44325362 is a 1,048,576-word by 36-bit synchronous quad data rate static RAM
fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
The
μ
PD44325082,
μ
PD44325092,
μ
PD44325182 and
μ
PD44325362 integrate unique synchronous peripheral
circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive
edge of K and /K.
These products are suitable for application which require synchronous operation, high speed, low voltage, high density
and wide bit configuration.
These products are packaged in 165-pin PLASTIC FBGA.
Features
1.8 ± 0.1 V power supply and HSTL I/O
DLL circuitry for wide output data valid window and future frequency scaling
Separate independent read and write data ports with concurrent transactions
100% bus utilization DDR READ and WRITE operation
Two-tick burst for low DDR transaction size
Two input clocks (K and /K) for precise DDR timing at clock rising edges only
Two output clocks (C and /C) for precise flight time and clock skew matching-clock
and data delivered together to receiving device
Internally self-timed write control
Clock-stop capability with
μ
s restart
User programmable impedance output
Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz)
Simple control logic for easy depth expansion
JTAG boundary scan
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| UPD44325092F5-E50-EQ2 | 36M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| UPD44325182F5-E50-EQ2 | 36M-BIT QDRII SRAM 2-WORD BURST OPERATION |
| UPD444004LE-10 | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
| UPD444004 | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
| UPD444004LE-12 | 4M-BIT CMOS FAST SRAM 1M-WORD BY 4-BIT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD44325084BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325092BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:SRAM Chip Sync Dual 1.8V 36M-Bit 4M x 9-Bit 0.45ns 165-Pin BGA |
| UPD44325094BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325094BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:IC SRAM QDRII 36MBIT 165BGA |
| UPD44325182BF5-E33-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。