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參數(shù)資料
| 型號： | UPD44323362F1-C40-FJ1 |
| 廠商： | NEC Corp. |
| 英文描述： | 32M-BIT CMOS SYNCHRONOUS FAST STATIC RAM 1M-WORD BY 36-BIT HSTL INTERFACE / REGISTER-REGISTER / LATE WRITE |
| 中文描述： | 32兆位CMOS同步快速靜態(tài)RAM的100萬字的36位HSTL接口/寄存器間/晚寫 |
| 文件頁數(shù)： | 19/28頁 |
| 文件大小： | 252K |
| 代理商： | UPD44323362F1-C40-FJ1 |
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19
Data Sheet M16379EJ4V0DS
μ
PD44323362
JTAG Instructions
Instructions
Description
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is to be executed whenever the instruction
register, whatever length it may be in the device, is loaded with all logic 0s. EXTEST is not implemented
in this device. Therefore this device is not 1149.1 compliant. Nevertheless, this RAMs TAP does
respond to an all zeros instruction, as follows. With the EXTEST (000) instruction loaded in the
instruction register the RAM responds just as it does in response to the SAMPLE instruction, except the
RAM output are forced to high impedance any time the instruction is loaded.
The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in
capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The
IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in
the test-logic-reset state.
The BYPASS instruction is loaded in the instruction register when the bypass register is placed between
TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board
level scan path to be shortened to facilitate testing of other devices in the scan path.
Sample is a Standard 1149.1 mandatory public instruction. When the sample instruction is loaded in the
instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input
and I/O buffers into the boundary scan register. Because the RAM clock(s) are independent from the
TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input
buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable
input will not harm the device, repeatable results cannot be expected. RAM input signals must be
stabilized for long enough to meet the TAPs input data capture setup plus hold time (t
CS
plus t
CH
). The
RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring
contents into the boundary scan register. Moving the controller to shift-DR state then places the
boundary scan register between the TDI and TDO pins. This functionality is not Standard 1149.1
compliant.
If the SAMPLE-Z instruction is loaded in the instruction register, all RAM outputs are forced to an inactive
drive state (high impedance) and the boundary register is connected between TDI and TDO when the
TAP controller is moved to the shift-DR state.
IDCODE
BYPASS
SAMPLE
SAMPLE-Z
JTAG Instruction Cording
IR2
IR1
IR0
Instruction
Note
0
0
0
EXTEST
1
0
0
1
IDCODE
0
1
0
SAMPLE-Z
1
0
1
1
BYPASS
1
0
0
SAMPLE
1
0
1
BYPASS
1
1
0
BYPASS
1
1
1
BYPASS
Note 1.
TRISTATE all data drivers and CAPTURE the pad values into a SERIAL SCAN LATCH.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| UPD44324362BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324362BF5-E40-FQ1-A | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
| UPD44324365BF5-E40-FQ1 | 制造商:Renesas Electronics Corporation 功能描述:36MB, DDRII SRAM - Trays 制造商:Renesas Electronics Corporation 功能描述:IC SRAM DDRII 36MBIT 165BGA |
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