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參數(shù)資料
| 型號： | UPD43256BGW-B15-9JL |
| 廠商： | NEC Corp. |
| 英文描述： | 256K-BIT CMOS STATIC RAM 32K-WORD BY 8-BIT |
| 中文描述： | 256K位CMOS靜態(tài)RAM 32K的詞8位 |
| 文件頁數(shù)： | 13/24頁 |
| 文件大?。?/td> | 174K |
| 代理商： | UPD43256BGW-B15-9JL |
13
μ
PD43256B
Write Cycle Timing Chart 1 (WE Controlled)
t
WC
t
CW
t
AW
t
WP
t
AS
t
WR
t
WHZ
t
DW
t
DH
t
OW
Indefinite data out
High
impe-
dance
High
impe-
dance
Data in
Indefinite data out
Address (Input)
CS (Input)
WE (Input)
I/O (Input/Output)
Cautions 1. CS or WE should be fixed to high level during address transition.
2. When I/O pins are in the output state, do not apply to the I/O pins signals that are opposite
in phase with output signals.
Remarks 1.
Write operation is done during the overlap time of a low level CS and a low level WE.
2.
When WE is at low level, the I/O pins are always high impedance. When WE is at high level,
read operation is executed. Therefore OE should be at high level to make the I/O pins high
impedance.
3.
If CS changes to low level at the same time or after the change of WE to low level, the I/O pins
will remain high impedance state.
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