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參數(shù)資料
| 型號(hào)： | UPD178P018GC |
| 廠商： | NEC Corp. |
| 英文描述： | CAT5E PATCH CABLES SNAGLESS,GREEN, 6 FT |
| 中文描述： | 8位單片機(jī) |
| 文件頁(yè)數(shù)： | 33/52頁(yè) |
| 文件大?。?/td> | 247K |
| 代理商： | UPD178P018GC |
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33
Data Sheet U12920EJ1V0DS00
μ
PD178F098
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCL cycle time
t
KCY7
R = 1 k
10
μ
s
SCL high-level width
t
KH7
C = 100 pF
Note
t
KCY7
– 160
ns
SCL low-level width
t
KL7
t
KCY7
– 50
ns
SDA0, SDA1 setup time (to SCL
↑
)
t
SIK7
200
ns
SDA0, SDA1 hold time
(from SCL
↓
)
t
KSI7
0
ns
SDA0, SDA1 output delay time
(from SCL
↓
)
t
KSO7
V
DD
= 4.5 to 5.5 V
0
300
ns
0
500
ns
SDA0, SDA1
↓
from SCL
↑
or
SDA0, SDA1
↑
from SCL
↑
t
KSB
200
ns
SCL
↓
from SDA0, SDA1
↓
t
SBK
400
ns
SDA0, SDA1 high-level width
t
SBH
500
ns
(vii) I
2
C Bus mode (SCL ... internal clock output)
Note
R and C are the load resistance and load capacitance of SCL, SDA0 and SDA1 output line.
(viii) I
2
C Bus mode (SCL ... external clock input)
Parameter
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
SCL cycle time
t
KCY8
1000
ns
SCL high-/low-level width
t
KH8,
t
KL8
400
ns
SDA0, SDA1 setup time (to SCL
↑
)
t
SIK8
200
ns
SDA0, SDA1 hold time
(from SCL
↓
)
t
KSI8
0
ns
SDA0, SDA1 output delay time
from SCL
↓
t
KSO8
R = 1 k
V
DD
= 4.5 to 5.5 V
0
300
ns
C = 100 pF
Note
0
500
ns
SDA0, SDA1
↓
from SCL
↑
or
SDA0, SDA1
↑
from SCL
↑
t
KSB
200
ns
SCL
↓
from SDA0, SDA1
↓
t
SBK
400
ns
SDA0, SDA1 high-level width
t
SBH
500
ns
SCL at rising or falling edge time
t
R8
, t
F8
1000
ns
Note
R and C are the load resistance and load capacitance of SDA0 and SDA1 output line.
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