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26
μ
PD17145(A1), 17147(A1), 17149(A1)
9. DATA BUFFER (DBF)
The data buffer consists of 4 nibbles allocated to addresses 0CH-0FH of BANK0 of the data memory.
This area is a data storage area that transfers data with the peripheral hardware of the CPU (address register,
serial interface, timers 0 and 1, and A/D converter) by using the GET or PUT instruction. Moreover, the constants
on the program memory can be read to the data buffer by using the MOVT DBF, @AR instruction.
9.1 Configuration of Data Buffer
Figure 9-1 shows the location of the data buffer on the data memory.
As shown in this figure, the data buffer is allocated addresses 0CH-0FH of the data memory, and consists
of a total of 16 bits or 4 nibbles (4
×
4 bits).
Figure 9-1. Location of Data Buffer
Figure 9-2 shows the configuration of the data buffer. As shown in this figure, the data buffer consists of 16
bits of the data memory, with the bit 0 of address 0FH as the LSB and bit 3 of address 0CH as the MSB.
Figure 9-2. Configuration of Data Buffer
Because the data buffer is located on the data memory, it can be manipulated by all the data memory
manipulation instructions.
0
F
1
2
3
4
5
6
7
8
9
A
B
C
D
E
0
1
2
3
4
5
6
7
Data memory
BANK0
Column address
Data buffer
(DBF)
System register (SYSREG)
R
Data memory
BANK0
0CH
0DH
0EH
0FH
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
3
b
2
b
1
b
0
b
11
b
10
b
9
b
8
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
b
15
b
14
b
13
b
12
DBF3
DBF2
DBF1
DBF0
S
B
M
S
B
L
Address
Bit
Bit
Symbol
Data
Data
Data buffer
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