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| 型號(hào)： | UPD17068GF-E |
| 廠商： | NEC Corp. |
| 英文描述： | 4-BIT SINGLE-CHIP MICROCONTROLLER CONTAINING IMAGE DISPLAY CONTROLLER AND PLL FREQUENCY SYNTHESIZER FOR DIGITAL TUNING SYSTEMS |
| 中文描述： | 4位單片機(jī)包含圖片顯示控制器和鎖相環(huán)頻率合成數(shù)字調(diào)諧系統(tǒng) |
| 文件頁(yè)數(shù)： | 119/341頁(yè) |
| 文件大?。?/td> | 1881K |
| 代理商： | UPD17068GF-E |
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119
μ
PD17068
11.7 OPERATION AFTER AN INTERRUPT IS ACCEPTED
When an interrupt is accepted, the following operations are performed, automatically and in the order
shown:
(1) The interrupt enable flip-flop and the interrupt request flag for the accepted interrupt request are reset
to 0. This indicates that the interrupt disable state is entered.
(2) The value in the stack pointer is decremented by one.
(3) The program counter contents are saved to the address stack register location specified by the stack
pointer.
The saved program counter contents indicate the program memory address subsequent to the address
at which the interrupt was accepted.
If the interrupt was accepted during the execution of a branch instruction, for example, the branch
destination address is indicated in the program counter. If the interrupt was accepted during the execution
of a subroutine call instruction, the called address is indicated. If the skip conditions are satisfied in a
skip instruction, the next instruction is executed as an NOP instruction, after which the interrupt is
accepted. In this case, the program counter indicates the address subsequent to the skipped instruction.
(4) The contents of the window register (WR), bank register (BANK), general-purpose register pointer (RP),
and program status word (PSWORD) are saved to the interrupt stack.
(5) The contents of the vector address generator for the accepted interrupt are transferred to the program
counter to branch to the interrupt handling routine.
For operations (1) to (5) above, a special one-instruction cycle (2
μ
s), that does not involve the execution
of a normal instruction, is required.
Such an instruction cycle is called an interrupt cycle.
This means that one instruction cycle (2
μ
s) is required to branch to the corresponding vector address after
the interrupt has been accepted.
11.8 RETURN FROM THE INTERRUPT HANDLING ROUTINE
To return control from the interrupt handling routine to the processing being performed when the interrupt
was accepted, the interrupt return instruction (RETI instruction) is used.
When the RETI instruction is executed, the following operations are performed, automatically and in the
order shown:
(1) The contents of the address stack register location, specified by the stack pointer, are restored to the
program counter.
(2) The interrupt stack contents are restored to the window register (WR), bank register (BANK), general-
purpose register pointer (RP), and program status word (PSWORD).
(3) The stack pointer value is incremented by one.
Operations (1) to (3) above are performed during the one instruction cycle (2
μ
s) in which the RETI instruction
is executed.
The RETI instruction differs from the RET and RETSK instructions, which are subroutine return instructions,
only in operation (2) above (system register restoration).
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