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參數(shù)資料
| 型號： | UPD16772B |
| 英文描述： | UPD16772B Data Sheet | Data Sheet[07/2002] |
| 中文描述： | UPD16772B數(shù)據(jù)表|數(shù)據(jù)表[07/2002] |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 157K |
| 代理商： | UPD16772B |
Data Sheet S15859EJ1V0DS
4
μ
PD160040
4. PIN FUNCTIONS
(1/2)
Pin Symbol
Pin Name
I/O
Description
S
1
to S
384
Driver
Output
The D/A converted 256-gray-scale analog voltage is output.
D
00
to D
07
Port 1 display data
Input
The display data is input with a width of 48 bits, viz., the gray scale data
D
10
to D
17
(8 bits) by 6 dots (2 pixels).
D
20
to D
27
D
X0
: LSB, D
X7
: MSB
D
30
to D
37
Port 2 display data
Input
D
40
to D
47
D
50
to D
57
R,/L
Shift direction control
Input
The shift direction control pin of shift register. The shift directions of the
shift registers are as follows.
R,/L = H (right shift): STHR input, S
1
→
S
384
, STHL output
R,/L = L (left shift): STHL input, S
384
→
S
1
, STHR output
These are the start pulse input/output pins when connected in cascade.
Loading of display data starts when a H level is read at the rising edge
of CLK.
A H level should be input at the pulse of one cycle of the clock signal.
If the start pulse input is more than 2 CLK, the first 1 CLK of the H-level
input is valid.
For right shift, STHR is input and STHL is output.
For left shift, STHL is input and STHR is output.
STHR
Right shift start pulse
I/O
STHL
Left shift start pulse
I/O
CLK
Shift clock
Input
The shift clock input pin of shift register. The display data is loaded into
the data register at the rising edge.
When 66-clock pulses are input after input of the start pulse, input of
display data is halted automatically. The contents of the shift register
are cleared at the STB’s rising edge.
STB
Latch
Input
The contents of the data register are transferred to the latch circuit at
the rising edge. In addition, at the falling edge, the gray scale voltage is
supplied to the driver. It is necessary to ensure input of one pulse per
horizontal period.
SRC
Through rate control
Input
SRC = H: High-through-rate period (large current consumption)
SRC = L: Low-through-rate period (small current consumption)
SRC is pulled up to the V
DD1
in the IC.
ORC
Output resistance control
Input
ORC = H: Low output resistance period
ORC = L: High output resistance period
ORC is pulled up to the V
DD1
in the IC.
POL
Polarity input
Input
POL = L: The S
2n
1
output uses V
0
-V
7
as the reference supply. The S
2n
output uses V
8
-V
15
as the reference supply.
POL = H: The S
2n
1
output uses V
8
-V
15
as the reference supply. The S
2n
output uses V
0
-V
7
as the reference supply.
S
2n
1
indicates the odd output and S
2n
indicates the even output. Input
of the POL signal is allowed the setup time (t
POL–STB
) with respect to
STB’s rising edge.
When it switches such as POL = H
→
L or L
→
H, all output pins are
output reset during STB = H. When it does not switch, all output pins
become Hi-Z (high impedance) during STB = H. Refer to
7.
RELATIONSHIP BETWEEN MODE, STB, SRC, ORC, POL, AND
OUTPUT WAVEFORM
for details.
#
#
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