參數(shù)資料
型號(hào)： UPC4741C(5)
英文描述： OP-AMP|QUAD|BIPOLAR|DIP|14PIN|PLASTIC
中文描述： 運(yùn)放|四|雙極|雙酯| 14PIN |塑料
文件頁(yè)數(shù)： 3/12頁(yè)
文件大?。?/td> 69K
代理商： UPC4741C(5)
Data Sheet G16051EJ3V0DS
3
μ
PC4741
μ
PC4741C, 4741G2
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, V
±
=
±
15 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input Offset Voltage
V
IO
R
S
≤
100
±
1.0
±
5.0
mV
Input Offset Current
Note
I
IO
±
30
±
50
nA
Input Bias Current
Note
I
B
70
300
nA
Large Signal Voltage Gain
A
V
R
L
≥
2 k
, V
O
=
±
10 V
25,000
50,000
Power Consumption
Pd
I
O
= 0 A, All Amplifiers
150
210
mW
Common Mode Rejection Ratio
CMR
80
100
dB
Supply Voltage Rejection Ratio
SVR
50
100
μ
V/ V
Maximum Output Voltage
V
om
R
L
≥
10 k
±
12
±
13.7
V
Maximum Output Voltage
V
om
R
L
≥
2 k
±
10
±
12.5
V
Common Mode Input Voltage Range
V
ICM
±
12
±
14
V
Slew Rate
SR
A
V
= 1
1.6
V/
μ
s
Input Equivalent Noise Voltage Density
e
n
f = 1 kHz
9
nV/ Hz
Channel Separation
f = 10 kHz
108
dB
Note
Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.
μ
PC4741C (5), 4741G2 (5)
ELECTRICAL CHARACTERISTICS (T
A
= 25°C, V
±
=
±
15 V)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Input Offset Voltage
V
IO
R
S
≤
100
±
1.0
±
2.0
mV
Input Offset Current
Note
I
IO
±
30
±
50
nA
Input Bias Current
Note
I
B
100
nA
Large Signal Voltage Gain
A
V
R
L
≥
2 k
, V
O
=
±
10 V
28,000
50,000
Power Consumption
Pd
I
O
= 0 A, All Amplifiers
150
210
mW
Common Mode Rejection Ratio
CMR
85
90
dB
Supply Voltage Rejection Ratio
SVR
50
μ
V/ V
Maximum Output Voltage
V
om
R
L
≥
10 k
±
12.5
±
13.7
V
Maximum Output Voltage
V
om
R
L
≥
2 k
±
11
±
12.5
V
Common Mode Input Voltage Range
V
ICM
±
13
±
14
V
Slew Rate
SR
A
V
= 1
1.6
V/
μ
s
Input Equivalent Noise Voltage Density
e
n
f = 1 kHz
9
nV/ Hz
Channel Separation
f = 10 kHz
108
dB
Note
Input bias currents flow out from IC. Because each currents are base current of PNP-transistor on input stage.
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