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MOS FIELD EFFECT TRANSISTOR
μ
PA2710GR
SWITCHING
P-CHANNEL POWER MOS FET
DATA SHEET
Document No. G15978EJ3V0DS00 (3rd edition)
Date Published February 2003 NS CP(K)
Printed in Japan
2002
DESCRIPTION
The
μ
PA2710GR is P-Channel MOS Field Effect Transistor
designed for power management applications of notebook
computers and Li-ion battery protection circuit.
FEATURES
Low on-state resistance
R
DS(on)1
= 5.5 m
MAX. (V
GS
= –10 V, I
D
= –7.5 A)
R
DS(on)2
= 9.0 m
MAX. (V
GS
= –4.5 V, I
D
= –7.5 A)
R
DS(on)3
= 11 m
MAX. (V
GS
= –4.0 V, I
D
= –7.5 A)
Low C
iss
: C
iss
= 4300 pF TYP.
Small and surface mount package (Power SOP8)
ORDERING INFORMATION
PART NUMBER
PACKAGE
μ
PA2710GR
Power SOP8
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C, All terminals are connected.)
Drain to Source Voltage (V
GS
= 0 V)
V
DSS
–30
V
Gate to Source Voltage (V
DS
= 0 V)
V
GSS
m
20
m
15
m
100
2
V
Drain Current (DC)
Drain Current (pulse)
Note1
Total Power Dissipation
Note2
Total Power Dissipation
Note3
I
D(DC)
A
I
D(pulse)
A
P
T1
W
P
T2
2
W
Channel Temperature
T
ch
150
°C
Storage Temperature
Single Avalanche Current
Note4
Single Avalanche Energy
Note4
T
stg
–55 to + 150
°C
I
AS
15
22.5
A
E
AS
mJ
Notes 1.
PW
≤
10
μ
s, Duty Cycle
≤
1%
2.
Mounted on ceramic substrate of 1200 mm
2
x 2.2 mm
3.
Mounted on a glass epoxy board (1 inch x 1 inch x 0.8 mm), PW = 10 sec
4.
Starting T
ch
= 25°C, V
DD
= –15 V, R
G
= 25
, L = 100
μ
H, V
GS
= –20
→
0 V
Remark
Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible,
and quickly dissipate it once, when it has occurred.
PACKAGE DRAWING (Unit: mm)
1.27
0.12 M
6.0 ±0.3
4.4
0.40
+0.10
0.78 MAX.
0
1
1
0.8
0.5 ±0.2
0
+
–
5.37 MAX.
0.10
1
4
8
5
1, 2, 3
4
5, 6, 7, 8 : Drain
: Source
EQUIVALENT CIRCUIT
Source
Body
Diode
Gate
Drain
The mark
#
shows major revised points.
#