
1995, 1999
DATA SHEET
COMPOUND TRANSISTOR
μ
PA104
FEATURES
9 GHz CONFIGURABLE TRANSISTOR BASED OR/NOR CIRCUITRY
OUTSTANDING h
FE
LINEARITY
TWO PACKAGE OPTIONS:
μ
PA104B:
Studded ceramic package provides superior thermal dissipation
μ
PA104G:
Reduced circuit size due to 14-pin plastic SOP package for surface mounting
EXCELLENT FOR ANALOG ADDITIONS & FORMATION OF 2-INPUT OR/NOR GATES
DESCRIPTION AND APPLICATIONS
The
μ
PA104 is a user-configurable, Si bipolar transistor array for formation of high speed OR/NOR gates. Its
internal transistor configuration and external connection options allow the user considerable flexibility in its
application. Its high gain bandwidth product (f
T
= 9 GHz) make it applicable for electro-optical, signal processing,
cellular telephone systems, instrumentation, and high speed gigabit logic circuits.
ORDERING INFORMATION
PART NUMBER
PACKAGE
μ
PA104B-E1
14-pin ceramic package
μ
PA104G-E1
14-pin plastic SOP (225 mil)
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C)
SYMBOLS
PARAMETERS
UNITS
RATINGS
V
CBO
*
Collector to Base Voltage
V
15
V
CEO
*
Collector to Emitter Voltage
V
6
V
EBO
*
Emitter to Base Voltage
V
2.5
I
C
*
Collector Current
mA
40
P
T
Power Dissipation
μ
PA104B
μ
PA104G
mW
mW
650
350
T
J
Junction Temperature
μ
PA104B
μ
PA104G
°
C
°
C
200
125
T
STG
Storage Temperature
μ
PA104B
μ
PA104G
°
C
°
C
–55 to +200
–55 to +125
*
Absolute maximum ratings for each transistor.
HIGH FREQUENCY NPN TRANSISTOR ARRAY
Caution electro-static sensitive devices
Document No. P10709EJ2V0DS00 (2nd edition)
Date Published October 1999 N CP(K)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
The mark
shows major revised points.