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參數(shù)資料
| 型號(hào)： | UMA1018M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | XO, clock |
| 英文描述： | Low-voltage dual frequency synthesizer for radio telephones |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1250 MHz, PDSO20 |
| 文件頁(yè)數(shù)： | 11/20頁(yè) |
| 文件大小： | 166K |
| 代理商： | UMA1018M |
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1995 Jun 27
11
Philips Semiconductors
Product specification
Low-voltage dual frequency
synthesizer for radio telephones
UMA1018M
Note
1.
I is the change in DAC output current when making the code transitions: 3FH/40H or 1FH/20H.
SERIAL BUS TIMING CHARACTERISTICS
V
DD
= V
CC
= 3 V; T
amb
= 25
°
C unless otherwise specified.
Note
1.
The minimum pulse width (t
W
) can be smaller than 4
μ
s provided all the following conditions are satisfied:
a) Principal main divider input frequency
b) Auxiliary main divider input frequency
c) Reference divider input frequency
DAC output signal levels; pin 10; R
ext
= 12 to 24 k
I
DAC
V
10
I
10min
I
monot
DAC full scale output current
output voltage compliance
minimum DAC current
worst case monotonicity test:
2
I
SET
1.5
×
I
SET
0
0.1
2
×
I
SET
2
2.5
×
I
SET
V
DD
0.4 V
5
1.9
mA
all codes
00 code
note 1
μ
A
Lock detect output signal; pin 20; open-drain output
V
OL
LOW level output voltage
I
sink
= 0.4 mA
0.4
V
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
t
r
t
f
T
cy
input rise time
input fall time
clock period
100
10
10
40
40
ns
ns
ns
Enable programming; E
t
START
t
END
t
W
t
SU;E
delay to rising clock edge
delay from last falling clock edge
minimum inactive pulse width
enable set-up time to next clock edge
40
20
4000
(1)
20
ns
ns
ns
ns
Register serial input data; DATA
t
SU;DAT
t
HD;DAT
input data to clock set-up time
input data to clock hold time
20
20
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
I
×
----128
×
f
VCO
t
W
256
>
f
AI
W
t
>
f
XTAL
t
W
3
>
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| UMA1018M/C3 | 制造商:NXP Semiconductors 功能描述: |
| UMA1019AM | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-voltage frequency synthesizer for radio telephones |
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