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參數(shù)資料
| 型號(hào)： | UMA1015M |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | XO, clock |
| 英文描述： | Low-power dual frequency synthesizer for radio communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO20 |
| 封裝： | PLASTIC, SOT-266A, SSOP-20 |
| 文件頁(yè)數(shù)： | 6/24頁(yè) |
| 文件大?。?/td> | 229K |
| 代理商： | UMA1015M |
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1
6
P
P
L
f
U
Table 2
Bit allocation
Note
1.
The test register should not be programmed with any other values except all zeros for normal operation.
FIRST
REGISTER BIT ALLOCATION
LAST
p1
dt16
X
MA16
0
MB16
p2
dt15 dt14
X
p3
p4
dt13 dt12
p5
p6
p7
p8
p9
p10
p11
p12
p13
dt4
p14
dt3
P2
p15
dt2
P1
p16
dt1
X
p17
dt0
X
MA0
R0
MB0
p18
p19
ADDRESS
0
1
1
1
0
p20
p21
DATA FIELD
CRB
X
VDON PO
OLA
OLB
SYNTHESIZER A MAIN DIVIDER COEFFICIENT
R11
REFERENCE DIVIDER COEFFICIENT
SYNTHESIZER B MAIN DIVIDER COEFFICIENT
RESERVED FOR TEST
(1)
CRA
X
sPDA sPDB P3
0
0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
SR
Table 3
Bit allocation description
Table 4
Out-of-lock select
SYMBOL
DESCRIPTION
sPDA, sPDB
P3, P2, P1 and P0
VDON
OLA, OLB
CRA, CRB
SR
software power-down for synthesizers A and B (0 = power-down)
bits output to pins 1, 2, 9 and 19 (1 = high impedance)
voltage doubler enable (1 = doubler enabled)
out-of-lock select; selects signal output to pin 19 (see Table 4)
charge pump A/B current to I
SET
ratio select (see Table 5)
reference frequency ratio select (see Table 6)
OLA
OLB
OUTPUT AT PIN 19
0
0
1
1
0
1
0
1
P0
lock status of loop B; OOLB
lock status of loop A; OOLA
logic OR function of loops A and B
Table 5
Charge pump current ratio
CRA/CRB
CURRENT AT PUMP
I
CP
= 12
×
I
SET
I
CP
= 24
×
I
SET
0
1
Table 6
Reference division ratio
SR
SYNTHESIZER A
SYNTHESIZER B
0
1
R
R
R
2R
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