參數(shù)資料
型號(hào): UMA1015M
廠商: NXP SEMICONDUCTORS
元件分類: XO, clock
英文描述: Low-power dual frequency synthesizer for radio communications
中文描述: PLL FREQUENCY SYNTHESIZER, 1100 MHz, PDSO20
封裝: PLASTIC, SOT-266A, SSOP-20
文件頁(yè)數(shù): 10/24頁(yè)
文件大?。?/td> 229K
代理商: UMA1015M
1995 Jun 22
10
Philips Semiconductors
Product specification
Low-power dual frequency synthesizer
for radio communications
UMA1015M
SERIAL TIMING CHARACTERISTICS
V
DD1
= 3 V; T
amb
= 25
°
C unless otherwise specified.
Logic input signal levels; DATA, CLK, E and HPD
V
IH
V
IL
I
bias
C
I
HIGH level input voltage
LOW level input voltage
input bias currents
input capacitance
at logic 1
at logic 0
at logic 1 or logic 0
indicative, not tested
0.7V
DD1
0.3
5
1
V
DD1
+ 0.3
0.3V
DD1
+5
V
V
μ
A
pF
Port outputs/Out-of-lock; P0/OOL, P1, P2, P3 and f
XTALO
- open drain outputs
V
OL
LOW level output voltage
I
sink
= 0.4 mA
0.4
V
SYMBOL
PARAMETER
MIN.
TYP.
MAX.
UNIT
Serial programming clock; CLK
t
r
, t
f
t
cy
input rise and fall times
clock period
100
10
40
ns
ns
Enable programming; E
t
START
t
END
t
W
t
SU;E
delay to rising clock edge
delay from last falling clock edge
minimum inactive pulse width
enable set-up time to next clock edge
40
20
4000
20
ns
ns
ns
ns
Register serial input data; DATA
t
SU;DAT
t
HD;DAT
input data to clock set-up time
input data to clock hold time
20
20
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Fig.3 Serial bus timing diagram.
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