參數(shù)資料
型號: UL62H1708AS1A55G1
元件分類: SRAM
英文描述: 128K X 8 STANDARD SRAM, 55 ns, PDSO32
封裝: 0.330 INCH, SOP-32
文件頁數(shù): 2/9頁
文件大小: 93K
代理商: UL62H1708AS1A55G1
2
November 01, 2001
UL62H1708A
Preliminary
Operating Mode
E1
E2
W
G
DQ0 - DQ7
Standby/not selected
*L*
*
High-Z
H
***
High-Z
Internal Read
L
H
High-Z
Read
L
H
L
Data Outputs Low-Z
Write
L
H
L
*
Data Inputs High-Z
Truth Table
Block Diagram
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
VCC
-0.3
4.6
V
Input Voltage
VI
-0.5
VCC + 0.5
V
Output Voltage
VO
-0.5
VCC + 0.5
V
Power Dissipation
PD
-1
W
Operating Temperature
K-Type
A-Type
Ta
-40
85
125
°C
Storage Temperature
Tstg
-65
150
°C
Output Short-Circuit Current
at VCC = 3.3 V and VO = 0 V
**
| IOS |100
mA
Characteristics
**Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of
≤ 5 ns, measured between 10 % and 90 % of V
I, as well as
input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VCC
VSS
W
G
E1
Ro
w
A
d
re
s
In
p
u
ts
Co
lu
m
n
A
d
re
s
In
p
u
ts
Address
Change
Detector
Co
lu
m
n
De
c
o
d
e
r
Ro
w
De
c
o
d
e
r
Sense Amplifier/
Write Control Logic
Clock
Generator
C
o
m
o
n
D
a
ta
I/O
Memory Cell
Array
1024 Rows x
128 x 8 Columns
A0
A1
A2
A3
A10
A5
A6
A7
A8
A9
A4
A11
A12
A13
A14
A15
A16
E2
* H or L
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