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參數(shù)資料
| 型號(hào)： | UL62H1708AS1A55G1 |
| 元件分類(lèi)： | SRAM |
| 英文描述： | 128K X 8 STANDARD SRAM, 55 ns, PDSO32 |
| 封裝： | 0.330 INCH, SOP-32 |
| 文件頁(yè)數(shù)： | 1/9頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | UL62H1708AS1A55G1 |
1
November 01, 2001
UL62H1708A
Preliminary
F 131072 x 8 bit static CMOS RAM
F 35 and 55 ns Access Time
F Common data inputs and
data outputs
F Three-state outputs
F Typ. operating supply current
35 ns: 45mA
55 ns: 30mA
F Standby current <100A at 125°C
F TTL/CMOS-compatible
F Power supply voltage 3.3 V
F Operating temperature range
-40 °C to 85 °C
-40 °C to 125 °C
F CECC 90000 Quality Standard
F ESD protection > 2000 V
(MIL STD 883C M3015.7)
F Latch-up immunity >100 mA
F Package: SOP32 (300/330 mil)
The UL62H1708A is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Standby
- Write
- Data Retention
The memory array is based on a
6-Transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs,
or
outputs,
are
active.
During the active state (E1 = L and
E2 = H) each address change
leads to a new Read or Write cycle.
In a Read cycle, the data outputs
are activated by the falling edge of
G, afterwards the data word will be
available at the outputs DQ0-DQ7.
After the address change, the data
outputs go High-Z until the new
information is available. The data
outputs have no preferred state. If
the memory is driven by CMOS
levels in the active state, and if
there is no change of the address,
data input and control signals W or
G, the operating current (IO = 0 mA)
drops to the value of the operating
current in the Standby mode. The
Read cycle is finished by the falling
edge of E2 or W, or by the rising
edge of E1, respectively.
Data retention is guaranteed down
to 2 V. With the exception of E1
and E2, all inputs consist of NOR
gates, so that no pull-up/pull-down
resistors are required.
Low Voltage Automotive Fast 128K x 8 SRAM
Pin Configuration
Top View
Signal Name
Signal Description
A0 - A16
Address Inputs
DQ0 - DQ7
Data In/Out
E1
Chip Enable 1
E2
Chip Enable 2
G
Output Enable
W
Write Enable
VCC
Power Supply Voltage
VSS
Ground
n.c.
not connected
Pin Description
1
n.c.
VCC
32
2
A16
A15
31
4
A12
W
29
5
A7
A13
28
3
A14
E2
30
6
A6
A8
27
7
A5
A9
26
8
A4
A11
25
12
A0
DQ7
21
9
A3
G
24
10
A2
A10
23
11
A1
E1
22
13
DQ0
DQ6
20
14
DQ1
DQ5
19
SOP
DQ4
DQ3
DQ2
VSS
18
17
15
16
Features
Description
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