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參數(shù)資料
| 型號(hào)： | UDA1321 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | USB-Digital To Analog Converters(通用串行總線-數(shù)模轉(zhuǎn)換器) |
| 中文描述： | 0.055 MHz, MICROCONTROLLER, PDIP32 |
| 文件頁(yè)數(shù)： | 31/44頁(yè) |
| 文件大?。?/td> | 280K |
| 代理商： | UDA1321 |
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1998 Oct 06
31
Philips Semiconductors
Preliminary specification
Universal Serial Bus (USB)
Digital-to-Analog Converter (DAC)
UDA1321
AC CHARACTERISTICS
V
DD
= 3.3 V; V
SS
= 0 V; T
amb
= 25
°
C; f
osc
= 48 MHz; f
s
= 44.1 kHz; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Driver characteristics D+ and D
(full-speed mode)
t
r
rise time
t
f
fall time
t
rf(m)
matching rise/fall time (t
r
/t
f
)
V
cr
output signal crossover voltage
R
(o)driver
driver output resistance
Data source timings D+ and D
(full-speed mode)
f
i(sample)
audio sample input frequency
f
fs(D)
full-speed data rate
t
fr
frame interval
t
J1(dif)
source differential jitter to next
transition
t
J2(dif)
source differential jitter for paired
transitions
t
W(EOP)
source End Of Packet (EOP) width
t
EOP(dif)
differential to EOP transition skew
t
JR1
receiver data jitter tolerance to next
transition
t
JR2
receiver data jitter tolerance for
paired transitions
t
EOPR1
EOP width at receiver must reject as
EOP
t
EOPR2
EOP width at receiver must accept
as EOP
C
L
= 50 pF
C
L
= 50 pF
4
4
90
1.3
28
20
20
110
2.0
43
ns
ns
%
V
steady-state drive
5
11.97
0.9995
3.5
12.00
1.0000
0.0
55
12.03
1.0005
+3.5
kHz
Mbits/s
ms
ns
4.0
0.0
+4.0
ns
160
2.0
18.5
0.0
175
+5.0
+18.5
ns
ns
ns
9.0
0.0
+9.0
ns
40
ns
82
ns
Serial input/output data timing;
see Fig.9
f
clk(sys)
f
i(WS)
t
r
t
f
t
BCK(H)
t
BCK(L)
t
s;DAT
t
h;DAT
t
s;WS
t
h;WS
system clock frequency
word select input frequency
rise time
fall time
bit clock HIGH time
bit clock LOW time
data set-up time
data hold time
word select set-up time
word select hold time
5
55
55
10
20
20
10
12
55
20
20
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
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