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參數(shù)資料
| 型號(hào)： | UDA1320 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Low-cost stereo filter DAC |
| 中文描述： | 低成本立體聲數(shù)模轉(zhuǎn)換器過濾器 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 102K |
| 代理商： | UDA1320 |
2000 Jan 10
5
Philips Semiconductors
Preliminary specification
Low-cost stereo filter DAC
UDA1320ATS
7
PINNING
8
FUNCTIONAL DESCRIPTION
8.1
System clock
The UDA1320ATS/N2 operates in slave mode only. This
means in all applications the system devices must provide
the system clock. The system frequency is selectable and
depends on the mode of operation.
The options are 256f
s
, 384f
s
and 512f
s
for the L3 mode
and 256f
s
plus 384f
s
for the static mode. The system clock
must be locked in frequency to the digital interface input
signals.
The UDA1320ATS/N2 supports sampling frequencies
from 16kHz up to 48kHz
8.2
Application modes
The application mode can be set with the tri-value
APPSEL pin, to L3 mode (APPSEL = V
SSD
) or to either of
two static modes (APPSEL = 0.5V
DDD
or
APPSEL = V
DDD
). See Table 1 for APPL0 to APPL3 pin
functions (active = HIGH).
Table 1
Selection modes via APPSEL (note 1)
For example, in static pin control mode, the output signal
can be soft muted by setting APPL0 HIGH. De-emphasis
can be switched on for 44.1 kHz by setting APPL1 HIGH.
APPL1 LOW will disable de-emphasis.
Note that when L3 interface is used, an L3 initialisation
must be done when the IC is powered up!
In L3 mode pin APPL0 must be set to LOW.
SYMBOL
PIN
DESCRIPTION
BCK
WS
DATAI
V
DDD
V
SSD
SYSCLK
APPSEL
APPL3
APPL2
APPL1
APPL0
V
REF(DAC)
V
DDA
V
O(L)
V
SSA
V
O(R)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
bit clock
word select
data input
digital power supply
digital ground
system clock: 256f
s
, 384f
s
, 512f
s
application mode select
application pin 3
application pin 2
application pin 1
application pin 0
DAC reference voltage
analog supply voltage
left output voltage
analog ground
right output voltage
Fig.2 Pin configuration.
handbook, halfpage
UDA1320A
MGM817
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VO(R)
BCK
VSSA
WS
VO(L)
DATAI
VDDA
VDDD
VREF(DAC)
VSSD
APPL0
SYSCLK
APPL1
APPSEL
APPL2
APPL3
PIN
APPSEL
V
SSD
0.5V
DDD
(384f
s
)
MUTE
DEEM
SF0
SF1
V
DDD
(256f
s
)
MUTE
DEEM
SF0
SF1
APPL0
APPL1
APPL2
APPL3
TEST
L3CLOCK
L3MODE
L3DATA
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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| UDA1320ATSN2 | 制造商:NXP Semiconductors 功能描述:1320ATS/N2 |
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