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參數(shù)資料
| 型號(hào)： | UDA1309H |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Low-power stereo bitstream ADC/DAC(低功耗立體聲位流ADC/DAC) |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP44 |
| 封裝： | PLASTIC, QFP-44 |
| 文件頁(yè)數(shù)： | 9/24頁(yè) |
| 文件大?。?/td> | 150K |
| 代理商： | UDA1309H |
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1998 Jan 06
9
Philips Semiconductors
Product specification
Low-power stereo bitstream ADC/DAC
UDA1309H
There are different modes in which the UDA1309H can operate. These modes can be selected as shown in Table 3 and
Fig.5. In mode a, the digital filters clock is switched off. Switching over to one of the ADC active modes (b, c or d) initiates
a reset sequence of the digital filters. This mode should be activated immediately after power-on for at least 2 clock
periods.
Table 3
Operating mode selection
Note
1.
X = don’t care.
MODE
DESCRIPTION
DEVICE PIN LOGIC
ANLPTR
ADPON
DAPON
a
b
c
d
e
f
not used
record and playback
record only
record and analog loop-through
analog loop-through
playback only
reserved
0
0
0
1
1
0
1
0
1
1
1
0
0
X
(1)
0
1
0
0
0
1
1
g and h
Fig.4 DAC and ADC data formats (continued from Fig.3).
handbook, full pagewidth
BCK
WS
SDA
BCK
WS
SDA
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LSB
MSB
LEFT
LEFT
RIGHT
RIGHT
LSB JUSTIFIED 48fs 16-BIT
I
2
S 48fs 16-BIT
(a)
(b)
MGE768
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