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參數資料
| 型號： | UCN5823 |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | BiMOS II 8-BIT SERIAL-INPUT, LATCHED DRIVERS |
| 中文描述： | BiMOS II 8位串行輸入，鎖存驅動 |
| 文件頁數： | 2/8頁 |
| 文件大?。?/td> | 163K |
| 代理商： | UCN5823 |
5821
AND
5822
8-BIT SERIAL-INPUT,
LATCHED DRIVERS
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
Copyright 1985, 2000, Allegro MicroSystems, Inc.
MOS
BIPOLAR
OUT
1
OUT
2
LOGIC
GROUND
STROBE
OUTPUT ENABLE
(ACTIVE LOW)
SERIAL
DATA OUT
5
7
6
Dwg. FP-013A
OUT
3
CLOCK
SERIAL
DATA IN
SERIAL-PARALLEL SHIFT REGISTER
LATCHES
V
DD
LOGIC
SUPPLY
1
2
3
16
OUT
6
OUT
7
OUT
8
15
14
11
10
9
OUT
4
OUT
5
13
12
8
4
POWER
GROUND
SUB
FUNCTIONAL BLOCK DIAGRAM
TYPICAL INPUT CIRCUITS
Dwg. No. A-14,314
Dwg. EP-010-3
IN
VDD
Dwg. EP-010-4A
IN
VDD
STROBE &
OUTPUT
ENABLE
CLOCK &
SERIAL
DATA IN
Number of Outputs ON
(I
OUT
= 200 mA
V
DD
= 12 V)
UCN5821A Max. Allowable Duty Cycle
at Ambient Temperature of
25
°
C
40
°
C
50
°
C
60
°
C
70
°
C
8
7
6
5
4
3
2
1
90%
100%
100%
100%
100%
100%
100%
100%
79%
90%
100%
100%
100%
100%
100%
100%
72%
82%
96%
100%
100%
100%
100%
100%
65%
74%
86%
100%
100%
100%
100%
100%
57%
65%
76%
100%
100%
100%
100%
Number of Outputs ON
(I
OUT
= 200 mA
V
DD
= 12 V)
UCN5821LW Max. Allowable Duty Cycle
at Ambient Temperature of
25
°
C
40
°
C
50
°
C
60
°
C
70
°
C
8
7
6
5
4
3
2
1
67%
77%
90%
100%
100%
100%
100%
100%
59%
68%
79%
95%
100%
100%
100%
100%
54%
62%
72%
86%
100%
100%
100%
49%
56%
65%
78%
98%
100%
100%
100%
43%
49%
57%
68%
86%
100%
100%
100%
TYPICAL OUTPUT DRIVER
OUT
SUB
7.2K
3K
NOTE — There is an indeterminate resistance between logic ground and power
ground. For proper operation, these terminals must be externally connected
together.
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