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參數(shù)資料
| 型號(hào)： | UCC3961DR |
| 英文描述： | Analog IC |
| 中文描述： | 模擬IC |
| 文件頁(yè)數(shù)： | 6/6頁(yè) |
| 文件大?。?/td> | 156K |
| 代理商： | UCC3961DR |
6
UCC1946
UCC2946
UCC3946
UNITRODE CORPORATION
7 CONTINENTAL BLVD. MERRIMACK, NH 03054
TEL. (603) 424-2410 FAX (603) 424-3460
0V
V
DD
t
1
0V
V
DD
V
DD
0V
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
T
RP
T
WP
RESET
WDI
WDO
Figure 6. Watchdog circuit timings.
APPLICATION INFORMATION (cont.)
t1:
Microprocessor is reset.
t2:
WDI is toggled some time after reset, but before
T
WP
expires.
t3:
WDI is toggled before T
WP
expires.
t4:
WDI is toggled before T
WP
expires.
t5:
WDI is not toggled before T
WP
expires and WDO
asserts low, triggering the microprocessor to enter an
error recovery routine.
t6:
The microprocessor’s error recovery routine is exe-
cuted and WDI is toggled, reinitiating the watchdog
timer.
t7:
WDI is toggled before T
WP
expires.
t8:
WDI is toggled before T
WP
expires.
t9:
RES is momentarily triggered, RES is asserted low
for T
RP
.
t10:
Microprocessor is reset, RES pulls high.
t11:
WDI is toggled some time after reset, but before
T
WP
expires.
t12:
WDI is toggled before T
WP
expires.
t13:
WDI is toggled before T
WP
expires.
t14:
V
DD
dips below the reset threshold, RES is as-
serted.
UDG-98007
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