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參數(shù)資料
| 型號： | UCC1919J |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Very low drop voltage regulators with inhibit |
| 中文描述： | 電源控制/管理 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 156K |
| 代理商： | UCC1919J |
UCC1946
UCC2946
UCC3946
SLUS247A - SEPTEMBER 1999
FEATURES
Fully Programmable Reset Threshold
Fully Programmable Reset Period
Fully Programmable Watchdog Period
2% Accurate Reset Threshold
VDD Can Go as Low as 2V
18
μ
A Maximum IDD
Reset Valid Down to 1V
Microprocessor Supervisor with Watchdog Timer
6
7
WDI
WP
8
VDD
3
RES
5
POWER TO
CIRCUITRY
A3
A2
A1
A0
CLK
CLR
8-BIT COUNTER
400nA
WDO
1
GND
EDGE DETECT
WATCHDOG TIMING
100mV
1.235V
2
RTH
4
RP
1.235V
.
400nA
POWER ON RESET
BLOCK DIAGRAM
Note: Pinout represents the 8-pin TSSOP package.
UDG-98001
DESCRIPTION
The UCC3946 is designed to provide accurate microprocessor supervi-
sion, including reset and watchdog functions. During power up, the IC
asserts a reset signal RES with VDD as low as 1V. The reset signal re-
mains asserted until the VDD voltage rises and remains above the re-
set threshold for the reset period. Both reset threshold and reset period
are programmable by the user. The IC is also resistant to glitches on
the VDD line. Once RES has been deasserted, any drops below the
threshold voltage need to be of certain time duration and voltage mag-
nitude to generate a reset signal. These values are shown in Figure 1.
An I/O line of the microprocessor may be tied to the watchdog input
(WDI) for watchdog functions. If the I/O line is not toggled within a set
watchdog period, programmable by the user, WDO will be asserted.
The watchdog function will be disabled during reset conditions.
The UCC3946 is available in 8-pin SOIC(D), 8-pin DIP (N or J) and
8-pin TSSOP(PW) packages to optimize board space.
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