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參數(shù)資料
| 型號： | UCC2895QTR |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | BiCMOS Advanced Phase Shift PWM Controller |
| 中文描述： | BiCMOS工藝先進(jìn)相移PWM控制器 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 291K |
| 代理商： | UCC2895QTR |
7
UCC1895
UCC2895
UCC3895
The Adaptive Delay Set feature (ADS) allows the user to
vary the delay times between switch commands within
each of the converter’s two legs. The delay time modula-
tion is implemented by connecting ADS (pin 11) to CS,
GND, or a resistive divider from CS to GND to set V
ADS
.
From the equation for V
DEL
above, if ADS is tied to GND
then V
DEL
rises in direct proportion to V
CS
, causing a de-
crease in t
DELAY
as the load increases. In this condition
the maximum value of V
DEL
is 2V. If ADS is connected to
a resistive divider between CS and GND the term
(V
CS
-V
DS
) becomes smaller, reducing the level of V
DEL
.
This will decrease the amount of delay modulation. In the
limit of ADS tied to CS, V
DEL
=0.5V and no delay modula-
tion occurs. In the case with maximum delay modulation
(ADS=GND), when the circuit goes from light load to
heavy load the variation of V
DEL
is from 0.5V to 2V. This
causes the delay times to vary by a 4:1 ratio as the load
is changed.
The ability to program an adaptive delay is a desirable
feature because the optimum delay time is a function of
the current flowing in the primary winding of the trans-
former, and can change by a factor of 10:1 or more as
circuit loading changes. Reference [1] delves into the
many interrelated factors for choosing the optimum delay
times for the most efficient power conversion, and illus-
trates an external circuit to enable adaptive delay set us-
ing the UC3879. Implementing this adaptive feature is
simplified in the UCC3895 controller, giving the user the
ability to tailor the delay times to suit a particular applica-
tion with a minimum of external parts.
[1]
L. Balogh,
Unitrode Power
Supply Design Seminar Manual, Unitrode Corporation,
1996, Topic 2.
APPLICATION INFORMATION (CONT.)
CLOCK
RAMP
&
COMP
PWM
SIGNAL
OUTPUT A
OUTPUT B
OUTPUT C
OUTPUT D
UDG-98138
0
0.5
1.0
100
1.5
2.0
2.5
200
300
400
500
A=1.0
A=0.8
A=0.6
A=0.4
A=0.2
A=0.1
CURRENT SENSE VOLTAGE (V)
D
A = V
ADS
/V
CS
R
DELAY
= 10k
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