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參數(shù)資料
| 型號(hào)： | UCC2884 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Frequency Foldback Current Mode PWM Controller |
| 中文描述： | 頻率折返電流模式PWM控制器 |
| 文件頁(yè)數(shù)： | 5/8頁(yè) |
| 文件大?。?/td> | 267K |
| 代理商： | UCC2884 |
5
UCC1884
UCC2884
UCC3884
Theory of Operation
The UCC3884 current mode PWM controller contains a
programmable oscillator which includes the ability to
synchronize multiple PWMs. The positive and negative
sloped portions of the oscillator waveform (measured at
CT), have time intervals that are set by external resistors
at ION and IOFF. The operating frequency is inversely
proportional to the timing capacitor. The negative sloped
portion of the oscillator waveform is extended in time as
the
measured
output
voltage
protection during output faults. The power supply output
voltage and the voltage from VREF are fed back to
VOUT. When the output voltage decreases, the voltage
at VOUT also decreases. As VOUT decreases below
3.5V, the operating frequency decreases. This reduction
in frequency allows the duty cycle to decrease below
what the CS to OUT delay would otherwise permit. This
is referred to as frequency foldback. An output short
circuit or overload causes the converter to enter the
frequency foldback mode. Synchronization to other
controllers can only occur during normal operation, that
is, when VOUT is greater than 3.0V.
decreases
providing
GT is provided to turn off an external depletion-mode
MOSFET after startup when the bootstrap winding
exceeds 10V. This depletion-mode MOSFET is used in
the housekeeping section of the converter to simplify
startup biasing circuitry. The amplifier that drives this
MOSFET has 300mV of hysteresis to avoid oscillation
during power up.
An
clamps the duty cycle. The duty cycle limit is inversely
proportional to input voltage and a resistor divider
network is used to program the proportionality constant.
At a given input voltage and constant load, under closed
loop control, the operating duty cycle is a fixed value.
The volt-second clamp duty cycle may then be set
somewhat higher than this operating duty cycle. For
other input voltages, the volt-second clamp will still
exceed the steady state operating duty cycle. This allows
normal closed loop operation of the converter. It is during
accurate
programmable
volt-second
technique
a load transient (a fault such as a momentary short
circuit) as the error amplifier increases the duty cycle,
that when the volt-second clamp accurately limits the
maximum
volt-seconds.
transformer does not saturate during a fault which can
fail the power supply. After the fault is removed the
converter resumes closed loop control.
This
ensures
that
the
CSS is provided which allows the UCC3884 to be
disabled with an external transistor. The increasing pulse
width at OUT during soft start should be programmed to
be less than the pulse width of the duty cycle limit that
the frequency foldback circuitry creates. The frequency
foldback circuit will be in effect during soft start since the
output voltage fed back to VOUT is less than 3.5V.
Designing the circuit in this fashion allows a proper
startup sequence.
The current sense feedback pin has an overcurrent
protection feature which forces a soft start cycle only if
the IC is not currently in a soft start cycle. A 1V bias at
the PWM comparator’s non-inverting input and a reset
dominant PWM latch permit zero duty cycle operation.
The error amplifier has a wide gain-bandwidth product
and its non-inverting input is internally set to 2.5VDC.
Oscillator
The oscillator has charge and discharge currents pro-
grammed with resistors to ground from ION and IOFF re-
spectively, as seen on the Oscillator Block Diagram (Fig.
1). This generates a linear sawtooth waveform on CT.
Frequency foldback is accomplished by the level shifted
output voltage controlling the VOUT voltage which de-
creases the discharge current and the frequency.
Synchronization is accomplished by coupling the fastest
oscillator CLKSYNC signal as shown on the Oscillator
Synchronization Diagram (Fig. 2). The fastest (master)
CLKSYNC pin will couple a negative pulse into the
slower (slave) CLKSYNC pins forcing the slaves’ CT pins
to quickly discharge as shown on the Oscillator Wave-
form diagram (Fig. 3).
APPLICATION INFORMATION
VREF:
This pin is the output of the 5V regulated
reference. Bypass this pin with a low ESR and ESL
ceramic capacitor (e.g., 0.47
μ
F).
VVS:
Provides a programmable duty cycle clamp which
is dependent upon the input voltage. A resistor divider
network reduces the input voltage supplied to VVS. The
IC determines the reciprocal of the voltage at VVS and
scales the result. The voltage is then compared to the
oscillator waveform to clamp the duty cycle. The purpose
of this clamp is to reduce the likelihood of saturating the
isolation transformer during unusual line or load condi-
tions.
PIN DESCRIPTIONS (cont.)
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