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參數(shù)資料
| 型號： | UCC2884 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Frequency Foldback Current Mode PWM Controller |
| 中文描述： | 頻率折返電流模式PWM控制器 |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 267K |
| 代理商： | UCC2884 |
4
UCC1884
UCC2884
UCC3884
CLKSYNC:
An edge triggered active low TTL signal to
this pin synchronizes the oscillator to an external clock.
When VOUT decreases below 3.0V, the frequency
foldback circuit is activated and the controller becomes
unsynchronized.
When
VOUT
controller resynchronizes to the external clock.
exceeds
3.0V,
the
COMP:
The output of the voltage error amplifier used for
compensation. The output is clamped to 3.0V minimum.
CS:
Current sense input. This pin accepts a voltage
proportional to converter inductor current. The voltage at
CS is compared to the output of the compensated error
amplifier to control the on-time of the switch. Voltage
mode control can be realized by driving this pin with a
fixed sawtooth ramp. Voltage feedforward is achieved by
making the peak of this ramp proportional to the input
voltage.
CSS:
A capacitor, C
SS
, to ground programs the soft start
time for the power up sequence. This function is also
used when an overcurrent fault occurs. As CSS is
charged, the PWM comparator uses the lowest of either
the voltage at CSS or the error amplifier output voltage to
determine the duty cycle. The duty cycle, therefore,
slowly increases during the soft start cycle. The faults
that cause CSS to discharge and shutdown the controller
are the logical OR of VREF below 4.4V or VDD below
8.8V. If a fault is still present when CSS is discharged
below 0.5V, the supply remains off until the fault is
cleared. The soft start time is determined by:
=3.5 C
I
SS
T
SS
SS
where I
SS
is 20
μ
A. A current limit terminates the present
cycle. It does not generate a soft start cycle.
CT:
discharged
waveform varies between 1.5V and 3.5V. The operating
frequency is determined by:
4.4
R
1.5
3.5
A
capacitor,
creating
C
T
to
ground,
oscillator
is
waveform.
charged
and
This
the
f =
C
+R
T
ON
OFF
The ratio of the time duration of the positive sloped
portion of the CT voltage waveform to the period gives
the maximum duty cycle.
FB:
The inverting input of the voltage amplifier used to
sense the output voltage. The non-inverting input of the
error amplifier is internally connected to 2.5V.
GND:
The ground pin internally used for all the amplifiers
and
as
the
return
for
all
connections to the UCC3884.
resistor
and
capacitor
GT:
Used to drive an external depletion-mode MOSFET
for the housekeeping power supply. The MOSFET is
turned off when the bootstrap winding voltage exceeds
10V. There is 300mV of hysteresis around the 10V
turn-off voltage to prevent oscillation. See Typical
Application.
IOFF:
A resistor, R
OFF,
to ground, programs the
discharge current of the timing capacitor C
T
. This is a
variable discharge current which determines the negative
slope of the oscillator voltage waveform at CT.
discharge time is dependent on the voltage at the VOUT
pin.
The
discharge
current
VOUT/R
OFF
. The VOUT pin is internally clamped to 3.5V
maximum.
The
is
given
by
I
OFF
=
ION:
A resistor, R
ON,
to ground programs the charge
current of the timing capacitor, C
T
, which generates the
positive slope of the oscillator waveform. The charge
time is constant and corresponds to the maximum output
on-time at OUT. The charge current equation is I
ON
=
1.5V/R
ON
. When required the linear positive slope of the
C
T
voltage could be buffered and used to provide slope
compensation into the CS pin.
OUT:
The output of the controller. The peak source
current is 0.5A and the peak sink current is 1.0A. The
faults listed under the CSS description turn off this
output.
PGND:
The power ground pin is used as the return for
the output transistor drive stage.
VDD:
The input voltage of the chip. A low ESR and ESL
ceramic capacitor from this pin to GND should be used
to bypass internal switching transients.
VOUT:
This pin accomplishes frequency foldback by
controlling the discharge current for the oscillator C
T
capacitor. A dc voltage proportional to the output voltage
is connected to this pin. To startup with zero output
voltage the user should tie a resistor between VREF and
VOUT. The value depends on the lowest desired
operating frequency. When VOUT decreases below 3.5V
the frequency decreases by reducing the discharge
current I
OFF
. When VOUT increases, the frequency
increases by increasing the discharge current. The
maximum operating frequency occurs when VOUT =
3.5V.
The C
T
charge time is constant to guarantee a
maximum output duty cycle. This pin must be above
3.0V to allow synchronization to occur.
PIN DESCRIPTIONS
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