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參數(shù)資料
| 型號： | UCC2580J-4 |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | Very low drop voltage regulators with inhibit |
| 中文描述： | 模擬IC |
| 文件頁數(shù)： | 5/10頁 |
| 文件大?。?/td> | 395K |
| 代理商： | UCC2580J-4 |
5
UCC1580-1,-2,-3,-4
UCC2580-1,-2,-3,-4
UCC3580-1,-2,-3,-4
UVLO and Startup
For self biased off-line applications, -2 and -4 versions
(UVLO on and off thresholds of 15V and 8.5V typical)
are recommended. For all other applications, -1 and -3
versions provide the lower on threshold of 9V. The IC re-
quires a low startup current of only 160
μ
A when VDD is
under the UVLO threshold, enabling use of a large trickle
charge resistor (with corresponding low power dissipa-
tion) from the input voltage. VDD has an internal clamp
at 15V which can sink up to 10mA. Measures should be
taken not to exceed this current. For -2 and -4 versions,
this clamp must be activated as an indication of reaching
the UVLO on threshold. The internal reference (REF) is
brought up when the UVLO on threshold is crossed. The
startup logic ensures that LINE and REF are above and
SHTDWN is
below their respective thresholds before
outputs are asserted. LINE input is useful for monitoring
actual input voltage and shutting off the IC if it falls be-
low a programmed value. A resistive divider should be
used to connect the input voltage to the LINE input. This
feature can protect the power supply from excessive
currents at low line voltages.
Figure 1. Output time relationships.
APPLICATION INFORMATION
UDG-95070-2
Note: Waveforms are not to scale.
SS:
A capacitor from SS to ground programs the soft
start time. During soft start, EAOUT follows the amplitude
of SS’s slowly increasing waveform until regulation is
achieved.
VDD:
Chip power supply pin. VDD should be bypassed
to PGND. The –1 and –3 versions require VDD to exceed
9V to start and remain above 8.5V to continue running. A
shunt clamp from VDD to GND limits the supply voltage
to 15V. The –2 and –4 versions do not start until the
shunt clamp threshold is reached and operation contin-
ues as long as VDD is greater than 8.5V.
PIN DESCRIPTIONS (cont.)
相關(guān)PDF資料 |
PDF描述 |
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| UCC2580Q-1 | Very low drop voltage regulators with inhibit |
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| UCC3588D | 5.0 AMP POSITIVE VOLTAGE REGULATOR |
| UCC3588DTR | 5.0 AMP POSITIVE VOLTAGE REGULATOR |
| UCC3588J | 5.0 AMP POSITIVE VOLTAGE REGULATOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UCC2580N-1 | 功能描述:電壓模式 PWM 控制器 Single Ended Active Clamp/Reset PWM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| UCC2580N-1G4 | 功能描述:電壓模式 PWM 控制器 Single Ended Active Clamp/Reset PWM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| UCC2580N-2 | 功能描述:電壓模式 PWM 控制器 Single Ended Active Clamp/Reset PWM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| UCC2580N-2G4 | 功能描述:電壓模式 PWM 控制器 Single Ended Active Clamp/Reset PWM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
| UCC2580N-3 | 功能描述:電壓模式 PWM 控制器 Single Ended Active Clamp/Reset PWM RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:1 拓?fù)浣Y(jié)構(gòu):Buck 輸出電壓:34 V 輸出電流: 開關(guān)頻率: 工作電源電壓:4.5 V to 5.5 V 電源電流:600 uA 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝 / 箱體:WSON-8 封裝:Reel |
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