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參數(shù)資料
| 型號(hào)： | UCC1858 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 基準(zhǔn)電壓源/電流源 |
| 英文描述： | High Efficiency, High Power Factor Preregulator |
| 中文描述： | 高效率，高功率因數(shù)前置穩(wěn)壓器 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大?。?/td> | 343K |
| 代理商： | UCC1858 |
8
UCC1858
UCC2858
UCC3858
Capacitor Ripple Reduction
For a power system where the PFC boost converter is
followed by a DC-DC converter stage, there are benefits
to synchronizing the two converters. In addition to the
usual advantages such as noise reduction and stability,
proper synchronization can significantly reduce the ripple
currents in the boost circuit’s output capacitor. Fig. 5
helps illustrate the impact of proper synchronization by
showing a PFC boost converter together with the simpli-
fied input stage of a forward converter. The capacitor cur-
rent during a single switching cycle depends on the
status of the switches Q1 and Q2 and is shown in Fig. 6.
It can be seen that with a synchronization scheme that
maintains conventional trailing edge modulation on both
converters, the capacitor current ripple is highest. The
greatest ripple current cancellation is attained when the
overlap of Q1 off-time and Q2 on-time is maximized. One
method of achieving this is to synchronize the turn-on of
the boost diode (D1) with the turn-on of Q2. This ap-
proach implies that the boost converter’s leading edge is
pulse width modulated while the forward converter is
modulated with traditional trailing edge PWM. The
UCC3858 is designed as a leading edge modulator with
easy synchronization to the downstream converter to fa-
cilitate this advantage. Table 1 compares the I
CBrms
for
D1/Q2 synchronization as offered by UCC3858 vs. the
I
CBrms
for the other extreme of synchronizing the turn-on
of Q1 and Q2 for a 200W power system with a V
BST
of
385V.
APPLICATION INFORMATION (cont.)
Figure 5. Simplified representation of a 2-stage PFC
power supply.
Figure 6. Timing waveforms for synchronization
scheme.
BOOST
DIODE
CURRENT
V
OUT
V
CT
V
CAO
4.5V
>1V
SLOPE=
I
CH
C
T
CLK
T
S
Figure 3c. Frequency foldback mode.
%
80
60
R
FBM
= 10k
FBL = VAO (V)
–1
–2
–3
0
–4
40
20
100
–5
–6
R
FBM
= 25k
R
FBM
= 100k
(R
T
= 24k, C
T
= 330pF, NOMINAL FREQUENCY 100kHz)
Figure 4. Frequency foldback characteristics.
Switch Sync
Trailing-Edge PWM for
both Boost and Buck
Inverted Switch Sync
Leading-Edge Boost PWM
Trailing-Edge Buck PWM
UDG-97131
UDG-97130-1
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