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參數(shù)資料
| 型號： | UCC1829J-1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.2 A SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 176K |
| 代理商： | UCC1829J-1 |
8
UCC1829-1/-2/-3
UCC2829-1/-2/-3
UCC3829-1/-2/-3
mately 3 VBE voltages) to determine if the reference is
alive. The undervoltage circuit either uses a user pro-
grammed level with a 16% hysteresis or an on threshold
equal to the VDD clamp voltage and an off threshold of
9V.
Once a fault occurs, a soft start cycle takes place. A fault
sets the fault latch. The Q output of the fault latch sets
the RS delay latch and turns on the 20
A soft start dis-
charge current sink. The Q output of the fault latch is
gated, however, by the output of the SS complete com-
parator. This insures that a SS cycle cannot start before
the previous one has finished. The soft start capacitor
then is discharged to 1V which is sensed by the RS delay
comparator. The fault latch is then reset. This in turn re-
sets the RS delay latch and turns off the 20
A current
sink and turns on a 20
A current source to charge the SS
capacitor.
The under voltage detection is set to a default value of
14V turn on (VDD clamp active value) and 9V turn off
when the UVLO pin is tied to GND. This default configu-
ration can be overridden by connecting a resistor divider
between VDD and GND to the UVLO pin. The hysteresis
for the user set threshold is 16%.
During undervoltage lockout, the self biasing outputs are
held "OFF" to prevent accidental turn-on of the power
switches.
Supply Section
The incoming voltage supply VDD is clamped by a shunt
VDD Clamp circuit at 14V.
VIN
VOUT
NINV
INV
EAO
U
T
PWCONT
RAM
P
RT
2
CT
RT
1
BI
SYNC
SS
1
2
3
20
19
4
5
6
7
8
9
10
11
12
14
15
16
17
18
13
CL
+
CL
-
PG
ND
OUT
B
OUT
A
VD
D
UVL
O
GND
LE
B
VR
EF
UCC3829-1
ISOLATED
FEEDBACK
DC SOURCE
OR RECTIFIED AC
BIAS
SUPPLY
TYPICAL APPLICATIONS
Figure 4. Push-Pull Converter Using UCC3829-1
UDG-98013
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