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參數(shù)資料
| 型號： | UCC1829J-1 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | 2.2 A SWITCHING CONTROLLER, 4000 kHz SWITCHING FREQ-MAX, CDIP20 |
| 封裝： | CERDIP-20 |
| 文件頁數(shù)： | 8/10頁 |
| 文件大?。?/td> | 176K |
| 代理商： | UCC1829J-1 |
7
UCC1829-1/-2/-3
UCC2829-1/-2/-3
UCC3829-1/-2/-3
Output Timing Configurations
The timing diagram shows the major differences between
the UCC3829-1, -2 and -3 parts.
The output of the
UCC3829-1 is a push-pull configuration with outputs A
and B 180° out of phase and with an output frequency
that is half of the CT’s waveform.
The UCC3829-2 produces dual outputs that are in phase
and can be used in situations that require high current
drive for single ended designs. A 0.5
resistor should be
added in series with each output before they are con-
nected together. The output pulse frequency is equal to
the CT waveform frequency in this case.
The output drive in the UCC3829-3 has a non-
overlapping complementary configuration. During each
clock cycle Output A produces an output pulse, followed
by a short delay, and then Output B produces an output
pulse. The short delay between Output A and Output B
pulses is tcd, the complementary delay time. This en-
sures that the outputs are never high simultaneously.
Leading Edge Blanking Section
The Leading Edge Blanking circuit provides a means to
insert a blanking period at the beginning of the cycle,
providing noise pulse elimination for current mode control
applications. This feature is similar to that of the UC3825
and UC3823A/B controllers. When enabled, an external
resistor is connected from LEB to VREF. An external ca-
pacitor is connected from LEB to either VREF or GND.
During the deadtime, LEB is pulled to GND. At the begin-
ning of the cycle, the pin is released and the capacitor
charges through the resistor toward VREF. At the thresh-
old VREF/2, a comparator senses the voltage and LEB is
removed. The leading edge blanking function can be dis-
abled by connecting LEB to VDD (> VREF). Leading
edge blanking is performed by the same MOSFET switch
connected to RAMP that is used for voltage feed forward
operation.
Current Timing and Protection
The current limit and overcurrent functions are accom-
plished using the pins CL+ and CL–. These two pins pro-
vide for differential current level sensing, with the trip
points referenced to CL–, rather than GND. The current
limit function provides a pulse by pulse current limiting,
whereas the overcurrent function is considered a fault
condition and initiates a fault logic soft start cycle.
The UCC3829 utilizes differential current sensing and
separate logic and power ground pins to eliminate some
of the noise issues of using current mode control. De-
vices with only one common ground pin for all stated
functions required the combination of power gate drive
current and low-level sensing currents in a common
trace. Since the current signal needed for control is em-
bedded in the power gate drive current, it is not enough
just to separate logic and power ground pins. Differential
sensing in UCC3829 referenced to the negative rail al-
lows the cleanest method of sensing current for use in a
peak current mode controlled power supply utilizing re-
sistive sensing. Current limiting is done on a cycle by cy-
cle basis when the typical threshold of 0.875V is
reached. If the fault level of 1.25V is reached a soft start
cycle is initiated. Internal circuitry insures that soft start
cycles are completed so that fault currents can be con-
trolled.
Fault Logic Section
The fault logic detects and handles various fault condi-
tions in the system. The output of the overcurrent com-
parator is logically ORed with the output combination of
the undervoltage detection circuit ORed with the output
of the VREF good circuit. The output of the precision ref-
erence voltage VREF is compared to a level (approxi-
tr
tf
tcd
UCC1829-3
OUT A
UCC 1829-3
OUT B
UCC1829-2
OUT B
UCC1829-2
OUT A
UCC1829-1
OUT B
UCC1829-1
OUT A
PWM CNTL
CT
BISYNC
TIMING DIAGRAMS
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