參數(shù)資料
型號: UCB1300BE
廠商: NXP SEMICONDUCTORS
元件分類: 調(diào)制器/解調(diào)器
英文描述: Advanced modem/audio analog front-end
中文描述: MODEM-SUPPORT CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-313-2, LQFP-48
文件頁數(shù): 49/56頁
文件大小: 1022K
代理商: UCB1300BE
1999 Jul 20
49
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
CONTROL REGISTER OVERVIEW
BIT
MODE
SYMBOL
REMARK
RESET
Address 0: I/O port data register
0 to 9
R/W
IO_DATA[n]
The bits in the write register provide the data of the I/O pin
when programmed as output.
The bits in the read register return the actual state of the
associated I/O pin.
0
Address 1: I/O port direction register
0 to 9
R/W
IO_DIR[n]
If '1', the associated I/O pin is defined as output.
If ‘0', the associated I/O pin is defined as input.
0
15
R/W
SIB_ZERO
If ‘1’, the SIBDOUT pin is forced ‘0’ during the second SIB
word.
If '0', the SIBDOUT pin is three-stated during the second SIB
word.
0
Address 2: Rising edge interrupt enable register
0 to 9
R/W
IO_RIS_INT[n]
If '1', the rising edge interrupt of the associated I/O pin is
enabled.
If '1', the rising edge interrupt of the adc_ready signal is
enabled.
If '1', the rising edge interrupt of the TSPX signal is enabled.
If '1', the rising edge interrupt of the TSMX signal is enabled.
If '1', the rising edge interrupt of the telecom clip is enabled.
If '1', the rising edge interrupt of the audio clip is enabled.
0
11
R/W
ADC_RIS_INT
0
12
13
14
15
R/W
R/W
R/W
R/W
TSPX_RIS_INT
TSMX_RIS_INT
TCLIP_RIS_INT
ACLIP_RIS_INT
0
0
0
0
Address 3: Falling edge interrupt enable register
0 to 9
R/W
IO_FAL_INT[n]
If '1', the falling edge interrupt of the associated I/O pin is
enabled.
If '1', the falling edge interrupt of the adc_ready signal is
enabled.
If '1', the falling edge interrupt of the TSPX signal is enabled.
If '1', the falling edge interrupt of the TSMX signal is enabled.
If '1', the falling edge interrupt of the telecom clip is enabled.
If '1', the falling edge interrupt of the audio clip is enabled.
0
11
R/W
ADC_FAL_INT
0
12
13
14
15
R/W
R/W
R/W
R/W
TSPX_FAL_INT
TSMX_FAL_INT
TCLIP_FAL_INT
ACLIP_FAL_INT
0
0
0
0
Address 4: Interrupt clear/status register
0 to 9
W
IO_INT_CLR[n]
A '0' to '1' transition clears the interrupt of the associated I/O
pin.
Returns the actual interrupt status of the associated I/O pin
A '0' to '1' transition clears the interrupt adc_ready signal.
Returns the actual interrupt status of the adc_ready signal.
0
R
W
R
IO_INT_STAT[n]
ADC_INT_CLR
ADC_INT_STAT
0
0
0
11
12
W
R
TSPX_INT_CLR
TSPX_INT_STAT
A '0' to '1' transition clears the interrupt of the TSPX signal.
Returns the actual interrupt status of the TSPX signal.
0
0
13
W
R
TSMX_INT_CLR
TSMX_INT_STAT
A '0' to '1' transition clears the interrupt of the TSMX signal.
Returns the actual interrupt status of the TSMX signal.
0
0
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