參數(shù)資料
型號: UCB1300BE
廠商: NXP SEMICONDUCTORS
元件分類: 調(diào)制器/解調(diào)器
英文描述: Advanced modem/audio analog front-end
中文描述: MODEM-SUPPORT CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, PLASTIC, SOT-313-2, LQFP-48
文件頁數(shù): 46/56頁
文件大?。?/td> 1022K
代理商: UCB1300BE
1999 Jul 20
46
Philips Semiconductors
Preliminary specification
Advanced modem/audio analog front-end
UCB1300
Notes
1.
2.
3.
4.
Additional test conditions: AUD_DIV[n] = 00001100; input signal 1 kHz, 90 mV (RMS); AUD_IN_ENA = 1.
Coding system for ADC output data is 2’s complement.
See Fig. 35.
Additional test conditions: AUD_DIV[n] = 00001100; 0 dB output attenuation; 90 % of digital full scale input voltage;
16
speaker connected.
Additional test conditions: TEL_DIV[n] = 0101000; 0 dB output attenuation; 90 % of digital full scale input voltage;
1200
load.
Coding system for DAC input data is 2’s complement.
See Fig. 36.
Additional test conditions: TEL_DIV[n] = 0101000; input signal 1 kHz, 300 mV (RMS); TEL_IN_ENA = 1;
TEL_VOICE_ENA = 0.
See Fig. 37.
See Fig. 38.
10. Deviation of the analog output from 0, with 0 code input to telecom output path.
11. The ADC cannot be started or armed if the touch screen circuit is set to interrupt mode (TSC_MODE[n] = 0,0).
12. Coding system for ADC is binary offset.
13. This is a requirement when an odd divisor is set in either the audio or the telecom codec.
14. This is valid for all SIB frame bits 0 to 63, except bits 17 to 20.
15. This is valid for a the SIB frame bits 17 to 20.
16. All curves repeat around the sample frequency f
sa
or f
st
for audio- respectively telecom codec.
17. Any touch-screen resistor above the maximum will not reach full scale and not saturate the ADC
18. The threshold can be used to verify a valid touch using pressure measurement.
5.
6.
7.
8.
9.
t
su(SIBSYNC-SIBCLK)
set-up time SIBSYNC to
SIBCLK falling edge
t
h(SIBSYNC-SIBCLK)
SIBSYNC hold time after
falling edge of SIBCLK
t
su(SIBDIN-SIBCLK)
set-up time SIBDIN to
SIBCLK falling edge
t
h(SIBDIN-SIBCLK)
SIBDIN hold time after
falling edge of SIBCLK
t
(SIBCLK-SIBDOUT)
rising edge of SIBCLK to
valid SIBDOUT
t
(SIBDIN-SIBDOUT)
valid SIBDIN to valid
SIBDOUT
-
15
-
ns
-
10
-
ns
-
15
-
ns
-
10
-
ns
note 14
-
10
-
ns
note 15
-
15
-
ns
Reset circuit
t
W(NRESET)
t
W(rst)
RESET pulse width
internal reset pulse width
5
-
5t
SIBCLK
-
-
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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