參數(shù)資料
型號： UCB1200
廠商： NXP Semiconductors N.V.
英文描述： Advanced modem/audio analog front-end
中文描述： 先進的調(diào)制解調(diào)器/音頻模擬前端
文件頁數(shù)： 19/54頁
文件大?。?/td> 1052K
代理商： UCB1200
1998 Jul 22
19
Philips Semiconductors
Product specification
Advanced modem/audio analog front-end
UCB1200
10 BIT ADC
The UCB1200 includes a 10 bit successive approximation analog to digital converter (ADC) with built-in track and hold
circuit and an analog multiplexer to select one of the 4 analog inputs (AD0 - AD3), the 4 touch screen inputs (TSPX,
TSMX, TSPY, TSMY) or the pressure output of the touch screen bias circuit. The ADC is used to read-out the touch
screen inputs and it measures the voltage on the four analog high voltage inputs AD0 - AD3. The analog multiplexer
contains 4 resistive dividers to attenuate the high voltage on the AD0 - AD3 inputs to the ADC input range.
The ADC is controlled completely through the SIB interface, but the UCB1200 contains internal logic to ease the control
of the ADC and to minimize the number of SIB frame read/write actions.
A complete ADC control sequence analog to digital conversion consists of several phases. Firstly the ADC has to be
enabled, secondly the input selector must be set to the proper input, thirdly the ADC conversion has to be started and
finally the ADC result has to be read from register 11.
The ADC is activated by setting ADC_ENA in register 10. The ADC circuit, including the track and hold circuit does not
consume any power as long as this bit is reset. The analog input multiplexer is controlled by ADC_INPUT[n] and the ADC
is actually started with the ADC_START bit. When TSPXand TSMX are in the interrupt mode, the ADC cannot be started,
even to measure AD0-3.
The UCB1200 has two different modes to start the ADC conversion, which are selected by the ADC_SYNC_ENA bit.
The default mode is the non-synchronization mode, in which the conversion is started directly with a 0->1 transition of
ADC_START. Secondly the ADC is started at a rising edge of the signal applied to the ADCSYNC pin if
ADC_SYNC_ENA is set.
The internal track and hold circuit requires a certain settling time to track the input signal correctly. This can be ensured
from the software by writing first a SIB frame with the ADC multiplexer setting before the SIB frame with the ADC_START
command is transferred. The UCB1200 ADC start/stop logic will detect whether the ADC input multiplexer is changed in
the same SIB frame as the ADC start command is given. In that case it will delay the actual start of the ADC circuit to
ensure that the track and hold settling time requirements are met. This leads to the following two timing diagrams:
Fig.13 Block diagram of the 10-bit ADC circuit.
internal reference
mux
9 to 1
track&hold
10 bit ADC
to control reg 11
10
ADC start
adcsync
stop logic
adc start
sync
enable
adc_sync_ena
相關PDF資料
PDF描述
UCB1200BE Advanced modem/audio analog front-end
UCB1300 Advanced modem/audio analog front-end
UCB1300BE Advanced modem/audio analog front-end
UCB1400BE Audio codec with touch screen controller and power management monitor
UCB1400 Audio codec with touch screen controller and power management monitor
相關代理商/技術參數(shù)
參數(shù)描述
UCB1200B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:UCB1200B
UCB1200BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced modem/audio analog front-end
UCB1300 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced modem/audio analog front-end
UCB1300BE 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced modem/audio analog front-end
UCB1400 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Audio codec with touch screen controller and power management monitor
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