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參數(shù)資料
| 型號(hào)： | UC62WV0256EI-70 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | Low Power CMOS SRAM 32K X8 Bits |
| 中文描述： | 低功耗CMOS SRAM 32K的X8位 |
| 文件頁(yè)數(shù)： | 7/10頁(yè) |
| 文件大小： | 465K |
| 代理商： | UC62WV0256EI-70 |
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
WRITE CYCLE2
(1,6)
t
WC
ADDRESS
t
DH
t
WHZ
WE
D
OUT
CE
t
CW
(11)
t
WP
(2)
t
AW
t
AS
D
IN
t
DW
t
OH
(8)
(7)
NOTES:
1. WE\ must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE\ and WE\ low. All signals
must be active to initiate a write and any one can terminate a write by going inactive. The data
input setup and hold timing should be referenced to the second transition edge of the signal that
terminates the write.
3. T
WR
is measured from the earlier of CE\ or WE\ going high at the end of write cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to
the outputs must not be applied.
5. If the CE\ low transition occurs simultaneously with the WE\ low transitions or after the WE\
transition, output remain in a high impedance state.
6. OE\ is continuously low (OE\ = V
IL
).
7. D
OUT
is the same phase of write data of this write cycle.
8. D
OUT
is the read data of next address.
9. If CE\ is low during this period, DQ pins are in the output state. Then the data input signals of
opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with C
L
= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE going low to the end of write.
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Revision 2.0
PAGE 7
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