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參數(shù)資料
| 型號(hào)： | UC62WV0256EI-70 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | DRAM |
| 英文描述： | Low Power CMOS SRAM 32K X8 Bits |
| 中文描述： | 低功耗CMOS SRAM 32K的X8位 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 465K |
| 代理商： | UC62WV0256EI-70 |
Low Power CMOS SRAM
32K X8 Bits
UC62WV0256
-35/-55/-70
DC ELECTRICAL CHARACTERISTICS (TA=-25
to 85
, VCC=2.0V to 5.6V)
Symbol
Comment
Guaranteed Input Low
Voltage
Guaranteed Input High
Voltage
Test Condition
MIN.
TYP.
(1)
MAX.
UNITS
V
IL
V
CC
=5.0V
-0.5
-
0.8
V
V
IH
V
CC
=5.0V
2.0
-
Vcc-0.2
V
I
L
Input Leakage Current
V
CC
=5.6V V
IN
=0V to V
CC
-
-
1
uA
I
OL
Output Leakage Current
V
CC
=5.6V CE\=V
IH
or OE\=V
IH
V
IO
=0V t V
CC
-
-
1
uA
V
OL
Output Low Voltage
V
CC
=5.6V, I
OL
=2mA
-
-
0.4
V
V
OH
Output High Voltage
V
CC
=3.0V, I
OH
=-1mA
2.4
-
-
V
I
CC
Operating Power Supply
Current
CE\=V
IL
,I
DQ
=0mA, F=Fmax
(3)
-
-
15
mA
I
SB1
TTL Standby Current
CE\=V
IH
, V
IN
=V
IH
to V
IL
-
-
1
mA
I
SB2
CMOS Standby Current
CE\
to 0.2V
V
CC
-0.2V, V
IN
=V
CC
-0.2V
-
2
4
uA
1. Typical characteristics are at TA = 25
.
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC, tRC=70ns .
DATA RETENTION CHARACTERISTICS ( TA=0
to 70
)
Symbol
Comment
Test Condition
MIN.
TYP.
(1)
MAX.
UNITS
V
DR
VCC to Data Retention
CE\
V
IN
CE\
V
IN
V
CC
- 0.2V
V
CC
-0.2V or V
IN
V
CC
- 0.2V
V
CC
-0.2V or V
IN
0.2V
1.2
-
-
V
I
CCDR
Data Retention Current
0.2V
-
0.5
1
uA
t
DR
Chip Deselect to Data
Retention Time
0
-
-
ns
t
R
Operation Recovery Time
See Retention Waveform
T
RC
(2)
-
-
ns
1.
V
CC
= 1.5V, TA = 25
.
2.
t
RC
= Read Cycle Time
LOW VCC DATA RETENTION WAVEFORM
(1)
(CE\ Controlled)
Data Retention Mode
V
DR
>= 1. 2V
t
CDR
t
R
VIH
VIH
CE >= V
CC
- 0. 2V
Vcc
CE
U-Chip Technology Corp. LTD.
Reserves the right to modify document contents without notice.
Revision 2.0
PAGE 3
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