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參數(shù)資料
| 型號(hào)： | U63764DK70G1 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | CapStore 8K x 8 nvSRAM |
| 中文描述： | CapStore 8K的× 8非易失 |
| 文件頁數(shù)： | 7/14頁 |
| 文件大小： | 146K |
| 代理商： | U63764DK70G1 |
U63764
7
March 31, 2006
STK Control #ML0055
Rev 1.0
Nonvolatile Memory Operations
Mode Selection
E
W
A12 - A0
(hex)
Mode
I/O
Power
Notes
H
X
X
Not Selected
Output High Z
Standby
L
H
X
Read SRAM
Output Data
Active
m
L
L
X
Write SRAM
Input Data
Active
L
H
0000
1555
0AAA
1FFF
10F0
0F0F
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile STORE
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
L
H
0000
1555
0AAA
1FFF
10F0
0F0E
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile RECALL
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
k, l
k, l
k, l
k, l
k, l
k, l
k:
The six consecutive addresses must be in order listed. W must be high during all six consecutive cycles. See STORE cycle and RECALL
cycle tables and diagrams for further details.
The following six-address sequence is used for testing purposes and should not be used: 0000, 1555, 0AAA, 1FFF, 10F0, 139C.
Activation of nonvolatile cycles does not depend on the state of G.
m: I/O state assumes that G
≤
V
IL
.
l:
No.
PowerStore
Power Up RECALL
Symbol
Conditions
Min.
Max.
Unit
Alt.
IEC
24
Power Up RECALL Duration
n
t
RESTORE
650
μ
s
25
STORE Cycle Duration
f, e
t
PDSTORE
10
ms
26
Time allowed to Complete SRAM Cycle
f
t
DELAY
1
μ
s
Low Voltage Trigger Level
V
SWITCH
4.0
4.5
V
n:
t
RESTORE
starts from the time V
CC
rises above V
SWITCH
.
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